Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)

2011 ◽  
Author(s):  
Pushkraj Tumne ◽  
Vikram Venkatadri ◽  
Santosh Kudtarkar ◽  
Michael Delaus ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Flip Chip ◽  
Bulk Solder ◽  
Consumer Electronics ◽  
Drop Test ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Wafer Level ◽  
Cross Sectional ◽  
Right Censored Data ◽  
Solder Balls

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
P. Tumne ◽  
V. Venkatadri ◽  
S. Kudtarkar ◽  
M. Delaus ◽  
D. Santos ◽  
...  
Keyword(s):  
Flip Chip ◽  
Consumer Electronics ◽  
Drop Test ◽  
Circuit Board ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Wafer Level ◽  
Cross Sectional ◽  
Right Censored Data ◽  
Solder Balls

Today’s consumer market demands electronics that are smaller, faster, and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer level chip scale package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence, the emphasis of reliability is shifting toward the study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and the bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the printed circuit board (PCB) by solder balls. The size of these solder balls is typically large enough (300 μm pre-reflow for 0.5-mm pitch and 250 μm pre-reflow for 0.4-mm pitch) to avoid the use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different silver (Ag) contents, backside lamination with different thicknesses, WLCSP type—direct and redistribution layer (RDL), bond pad thickness, and sputtered versus electroplated under bump metallurgy (UBM) deposition methods for 8 × 8, 9 × 9, and 10 × 10 array sizes. The test vehicles built using these design parameters were drop tested using Joint Electron Devices Engineering Council (JEDEC) recommended test boards and conditions as per JESD22-B11. Cross-sectional analysis was used to identify, confirm, and segregate the intermetallic and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data were collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and ungrouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Multi-Stacked Flip Chips with Copper Plated Through Silicon Vias and Re-distribution for 3D System-in-Package Integration

2006 ◽  
Vol 970 ◽  
Author(s):  
Shi-Wei Ricky Lee ◽  
Ronald Hon
Keyword(s):  
Flip Chip ◽  
Three Dimensional ◽  
Back Side ◽  
Wafer Level ◽  
Flip Chips ◽  
Electrical Interconnection ◽  
Solder Balls ◽  
Original Size ◽  
Structure Lead ◽  
Silicon Vias

ABSTRACTThe study is a prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs for interconnection. Three chips are stacked together to make a 3DP with solder bumped flip chips. TSVs are fabricated and distributed along the periphery of the middle chip. The TSVs are formed by dry etching, deep reactive ions etching (DRIE), with dimensions of 150 × 100 microns. The TSVs are plugged by copper plating. The filled TSVs are connected to the solder pads by extended pad patterns surrounding the top and the bottom of TSVs on both sides of the wafer for the middle chip. After pad patterning passivation and solder bumping, the wafer is sawed into chips for subsequent 3D stacked die assembly. Because the TSVs are located at the periphery of the middle chips and stretch across the saw street between adjacent chips, they will be sawed through their center to form two open TSVs (with half of the original size) for electrical interconnection between the front side and the back side of the middle chip. The top chip is made by the conventional solder bumped flip chip processes and the bottom chip is a carrier with some routing patterns. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented.

Reduction of Thermal Stress - Part II: Passivation Thickness Optimization of FLATPV Surface Bump Design

2017 ◽  
Vol 2017 (1) ◽  
pp. 000508-000512
Author(s):  
Raj Sekar Sethu ◽  
Salil Hari Kulkarni ◽  
How Ung Ha ◽  
Kok Heng Soon
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Passivation Layer ◽  
Fracture Rate ◽  
Thickness Optimization ◽  
Wafer Level ◽  
Passivation Layers ◽  
Solder Balls ◽  
Interaction Stress ◽  
Underfill Material

Abstract Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material. The flat passivation design can reduce the chip package interaction for underfill material but it needed to be evaluated numerically for wafer level stress before being touted as a solution towards reducing passivation cracks. In Part II of this series of papers, the flat passivation layer thicknesses were numerically simulated and modified using response surface methodology design of experiments (RSM DOE) techniques. The optimized passivation layer thickness showed decreased stress which was validated using a simulation confirmation run.

Pb-free v/s Tin-Lead Reliability Comparison for Telecom/High Reliability Applications

2010 ◽  
Vol 2010 (1) ◽  
pp. 000284-000293
Author(s):  
Ganesh Iyer ◽  
Gnyaneshwar Ramakrishna ◽  
Lavanya Gopalakrishnan ◽  
Kuo-Chuan Liu
Keyword(s):  
Service Providers ◽  
High Reliability ◽  
Consumer Electronics ◽  
Circuit Board ◽  
Evaluation Methodology ◽  
Mechanical Shock ◽  
Printed Circuit Board Assembly ◽  
Component Level ◽  
Cross Sectional ◽  
Free Solder

With the European Union's (EU's) RoHS directives coming into force in July 2006 for consumer electronics products, the transition to lead-free (Pb-free) solder has occurred at a rapid pace. This push has driven many OEM suppliers/manufacturers to adopt Pb-free solder and End of Life many of their conventional Tin-Lead (Sn-Pb) components. This has forced telecom or high reliability applications to adopt Pb-free solder compositions with many reliability anomalies unanswered. While there have been many studies published on long term reliability of Pb-free solder joints at the component level, there have been few studies focused on the time zero reliability of the joints at the printed circuit board assembly (PCBA) level. The goal of this study is to help the OEM suppliers and their customers (like service providers) to come up with a common PCBA test methodology that will help identify and weed out early, marginal manufacturing and design defects that would crop up due to transition to the Pb-free solder. A normalized reliability data comparison and impact of the test on Pb-free and Tin-Lead solder alloys using test vehicles is presented in this study. The sequential PCBA level evaluation methodology involves a series of tests that include Thermal Aging, Mechanical Shock, Vibration, Functional test over elevated temperature and Destructive Analysis (Dye & Pry and Cross-sectional analysis) . The solder joint reliability comparisons for different components are presented against this methodology using different PCBA constructions (test vehicles).

A New Method of Wafer Level Plan View TEM Sample Preparation by DualBeam

2008 ◽  
Author(s):  
Hyoung H. Kang ◽  
Michael A. Gribelyuk ◽  
Oliver D. Patterson ◽  
Steven B. Herschbein ◽  
Corey Senowitz
Keyword(s):  
Sample Preparation ◽  
Ex Situ ◽  
Wafer Level ◽  
Cross Sectional ◽  
Plan View ◽  
Manufacturing Line ◽  
Transmission Electron ◽  
Thin Lamella ◽  
Preparation Techniques

Abstract Cross-sectional style transmission electron microscopy (TEM) sample preparation techniques by DualBeam (SEM/FIB) systems are widely used in both laboratory and manufacturing lines with either in-situ or ex-situ lift out methods. By contrast, however, the plan view TEM sample has only been prepared in the laboratory environment, and only after breaking the wafer. This paper introduces a novel methodology for in-line, plan view TEM sample preparation at the 300mm wafer level that does not require breaking the wafer. It also presents the benefit of the technique on electrically short defects. The methodology of thin lamella TEM sample preparation for plan view work in two different tool configurations is also presented. The detailed procedure of thin lamella sample preparation is also described. In-line, full wafer plan view (S)TEM provides a quick turn around solution for defect analysis in the manufacturing line.

scholarly journals Research on the Computed Tomography Pebble Flow Detecting System for HTR-PM

2017 ◽  
Vol 2017 ◽  
pp. 1-13
Author(s):  
Xin Wan ◽  
Ximing Liu ◽  
Jichen Miao ◽  
Peng Cong ◽  
Yuai Zhang ◽  
...  
Keyword(s):  
Computed Tomography ◽  
Three Dimensional ◽  
Helical Ct ◽  
Design Parameters ◽  
Three Dimensional Model ◽  
Safe Operation ◽  
Cross Sectional ◽  
Ct System ◽  
Near Future ◽  
Pebble Flow

Pebble dynamics is important for the safe operation of pebble-bed high temperature gas-cooled reactors and is a complicated problem of great concern. To investigate it more authentically, a computed tomography pebble flow detecting (CT-PFD) system has been constructed, in which a three-dimensional model is simulated according to the ratio of 1 : 5 with the core of HTR-PM. A multislice helical CT is utilized to acquire the reconstructed cross-sectional images of simulated pebbles, among which special tracer pebbles are designed to indicate pebble flow. Tracer pebbles can be recognized from many other background pebbles because of their heavy kernels that can be resolved in CT images. The detecting principle and design parameters of the system were demonstrated by a verification experiment on an existing CT system in this paper. Algorithms to automatically locate the three-dimensional coordinates of tracer pebbles and to rebuild the trajectory of each tracer pebble were presented and verified. The proposed pebble-detecting and tracking technique described in this paper will be implemented in the near future.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

scholarly journals Design of an Ultra-Wideband Microstrip-to-Slotline Transition on Low-Permittivity Substrate

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1329
Author(s):  
Jung Seok Lee ◽  
Gwan Hui Lee ◽  
Wahab Mohyuddin ◽  
Hyun Chul Choi ◽  
Kang Wook Kim
Keyword(s):  
Microstrip Line ◽  
Return Loss ◽  
Analytical Formula ◽  
Parameter Tuning ◽  
Ultra Wideband ◽  
Design Parameters ◽  
Analytical Line ◽  
Cross Sectional ◽  
Analysis And Design ◽  
Low Permittivity

Analysis and design of an ultra-wideband microstrip-to-slotline transition on a low permittivity substrate is presented. Cross-sectional structures along the proposed transition are analyzed using conformal mapping assuming quasi-TEM modes, attaining one analytical line impedance formula with varying design parameters. Although the slotline is a non-TEM transmission line, the transitional structures are configured to have quasi-TEM modes before forming into the slotline. The line impedance is optimally tapered using the Klopfenstein taper, and the electric field shapes are smoothly transformed from microstrip line to slotline. The analytical formula is accurate within 5% difference, and the final transition configuration can be designed without parameter tuning. The implemented microstrip-to-slotline transition possesses insertion loss of less than 1.5 dB per transition and return loss of more than 10 dB from 4.4 to over 40 GHz.

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