Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
P. Tumne ◽  
V. Venkatadri ◽  
S. Kudtarkar ◽  
M. Delaus ◽  
D. Santos ◽  
...  
Keyword(s):  
Flip Chip ◽  
Consumer Electronics ◽  
Drop Test ◽  
Circuit Board ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Wafer Level ◽  
Cross Sectional ◽  
Right Censored Data ◽  
Solder Balls

Today’s consumer market demands electronics that are smaller, faster, and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer level chip scale package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence, the emphasis of reliability is shifting toward the study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and the bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the printed circuit board (PCB) by solder balls. The size of these solder balls is typically large enough (300 μm pre-reflow for 0.5-mm pitch and 250 μm pre-reflow for 0.4-mm pitch) to avoid the use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different silver (Ag) contents, backside lamination with different thicknesses, WLCSP type—direct and redistribution layer (RDL), bond pad thickness, and sputtered versus electroplated under bump metallurgy (UBM) deposition methods for 8 × 8, 9 × 9, and 10 × 10 array sizes. The test vehicles built using these design parameters were drop tested using Joint Electron Devices Engineering Council (JEDEC) recommended test boards and conditions as per JESD22-B11. Cross-sectional analysis was used to identify, confirm, and segregate the intermetallic and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data were collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and ungrouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)

2011 ◽  
Author(s):  
Pushkraj Tumne ◽  
Vikram Venkatadri ◽  
Santosh Kudtarkar ◽  
Michael Delaus ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Flip Chip ◽  
Bulk Solder ◽  
Consumer Electronics ◽  
Drop Test ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Wafer Level ◽  
Cross Sectional ◽  
Right Censored Data ◽  
Solder Balls

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Pb-free v/s Tin-Lead Reliability Comparison for Telecom/High Reliability Applications

2010 ◽  
Vol 2010 (1) ◽  
pp. 000284-000293
Author(s):  
Ganesh Iyer ◽  
Gnyaneshwar Ramakrishna ◽  
Lavanya Gopalakrishnan ◽  
Kuo-Chuan Liu
Keyword(s):  
Service Providers ◽  
High Reliability ◽  
Consumer Electronics ◽  
Circuit Board ◽  
Evaluation Methodology ◽  
Mechanical Shock ◽  
Printed Circuit Board Assembly ◽  
Component Level ◽  
Cross Sectional ◽  
Free Solder

With the European Union's (EU's) RoHS directives coming into force in July 2006 for consumer electronics products, the transition to lead-free (Pb-free) solder has occurred at a rapid pace. This push has driven many OEM suppliers/manufacturers to adopt Pb-free solder and End of Life many of their conventional Tin-Lead (Sn-Pb) components. This has forced telecom or high reliability applications to adopt Pb-free solder compositions with many reliability anomalies unanswered. While there have been many studies published on long term reliability of Pb-free solder joints at the component level, there have been few studies focused on the time zero reliability of the joints at the printed circuit board assembly (PCBA) level. The goal of this study is to help the OEM suppliers and their customers (like service providers) to come up with a common PCBA test methodology that will help identify and weed out early, marginal manufacturing and design defects that would crop up due to transition to the Pb-free solder. A normalized reliability data comparison and impact of the test on Pb-free and Tin-Lead solder alloys using test vehicles is presented in this study. The sequential PCBA level evaluation methodology involves a series of tests that include Thermal Aging, Mechanical Shock, Vibration, Functional test over elevated temperature and Destructive Analysis (Dye & Pry and Cross-sectional analysis) . The solder joint reliability comparisons for different components are presented against this methodology using different PCBA constructions (test vehicles).

Damage and Failures of CGA/BGA Assemblies Under Thermal Cycling and Dynamic Loadings

2013 ◽  
Author(s):  
Reza Ghaffarian
Keyword(s):  
Thermal Cycling ◽  
Mechanical Loading ◽  
Test Data ◽  
Printed Circuit Board ◽  
High Reliability ◽  
Circuit Board ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Space Applications ◽  
High Processing

Commercial-off-the-shelf column/ball grid array packaging (COTS CGA/BGA) technologies in high-reliability versions are now being considered for use in high-reliability electronic systems. For space applications, these packages are prone to early failure due to the severe thermal cycling in ground testing and during flight, mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of solder interconnections decreases, susceptibility to thermal, mechanical loading and cycling fatigue grows even more. This paper reviews technology as well as thermo-mechanical reliability of field programmable gate array (FPGA) IC packaging developed to meet demands of high processing powers. The FPGAs that generally come in CGA/PBGA packages now have more than thousands of solder balls/columns under the package area. These packages need not only to be correctly joined onto printed circuit board (PCB) for interfacing; they also should show adequate system reliability for meeting thermo-mechanical requirements of the electronics hardware application. Such reliability test data are rare or none for harsher environmental applications, especially for CGAs having more than a thousand of columns. The paper also presents significant test data gathered under thermal cycling and drop testing for high I/O PBGA/CGA packages assembled onto PCBs. Damage and failures of these assemblies after environmental exposures are presented in detail. Understanding the key design parameters and failure mechanisms under thermal and mechanical conditions is critical to developing an approach that will minimize future failures and will enable low-risk insertion of these advanced electronic packages with high processing power and in-field re-programming capability.

Multi-Stacked Flip Chips with Copper Plated Through Silicon Vias and Re-distribution for 3D System-in-Package Integration

2006 ◽  
Vol 970 ◽  
Author(s):  
Shi-Wei Ricky Lee ◽  
Ronald Hon
Keyword(s):  
Flip Chip ◽  
Three Dimensional ◽  
Back Side ◽  
Wafer Level ◽  
Flip Chips ◽  
Electrical Interconnection ◽  
Solder Balls ◽  
Original Size ◽  
Structure Lead ◽  
Silicon Vias

ABSTRACTThe study is a prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs for interconnection. Three chips are stacked together to make a 3DP with solder bumped flip chips. TSVs are fabricated and distributed along the periphery of the middle chip. The TSVs are formed by dry etching, deep reactive ions etching (DRIE), with dimensions of 150 × 100 microns. The TSVs are plugged by copper plating. The filled TSVs are connected to the solder pads by extended pad patterns surrounding the top and the bottom of TSVs on both sides of the wafer for the middle chip. After pad patterning passivation and solder bumping, the wafer is sawed into chips for subsequent 3D stacked die assembly. Because the TSVs are located at the periphery of the middle chips and stretch across the saw street between adjacent chips, they will be sawed through their center to form two open TSVs (with half of the original size) for electrical interconnection between the front side and the back side of the middle chip. The top chip is made by the conventional solder bumped flip chip processes and the bottom chip is a carrier with some routing patterns. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented.

Effects of Corner/Edge Bonding and Underfill Properties on the Thermal Cycling Performance of Lead Free Ball Grid Array Assemblies

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
P. Borgesen ◽  
D. Blass ◽  
M. Meilunas
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Ball Grid Array ◽  
Cycling Performance ◽  
Circuit Board ◽  
Lead Free ◽  
Sac305 Solder ◽  
Solder Balls ◽  
Selection Of

Underfilling will almost certainly improve the performance of an area array assembly in drop, vibration, etc. However, depending on the selection of materials, the thermal fatigue life may easily end up worse than without an underfill. This is even more true for lead free than for eutectic SnPb soldered assemblies. If reworkability is required, the bonding of the corners or a larger part of the component edges to the printed circuit board (PCB), without making contact with the solder joints, may offer a more attractive materials selection. A 30 mm flip chip ball grid array (FCBGA) component with SAC305 solder balls was attached to a PCB and tested in thermal cycling with underfills and corner/edge bonding reinforcements. Two corner bond materials and six reworkable and nonreworkable underfills with a variety of mechanical properties were considered. All of the present underfills reduced the thermal cycling performance, while edge bonding improved it by up to 50%. One set of the FCBGAs was assembled with a SnPb paste and underfilled with a soft reworkable underfill. Surprisingly, this improved the thermal cycling performance slightly beyond that of the nonunderfilled assemblies, providing up to three times better life than for those assembled with a SAC305 paste.

On the Way from Fan-out Wafer to Fan-out Panel Level Packaging

2016 ◽  
Vol 2016 (S2) ◽  
pp. S1-S23 ◽  
Author(s):  
Karl-Friedrich Becker ◽  
Tanja Braun ◽  
S. Raatz ◽  
M. Minkus ◽  
V. Bader ◽  
...  
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Layer Structure ◽  
Form Factors ◽  
Circuit Board ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Bga Packages ◽  
Wire Bonds ◽  
Near Future

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Manufacturing is currently done on wafer level up to 12″/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18″×24″ or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed.

Reduction of Thermal Stress - Part II: Passivation Thickness Optimization of FLATPV Surface Bump Design

2017 ◽  
Vol 2017 (1) ◽  
pp. 000508-000512
Author(s):  
Raj Sekar Sethu ◽  
Salil Hari Kulkarni ◽  
How Ung Ha ◽  
Kok Heng Soon
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Passivation Layer ◽  
Fracture Rate ◽  
Thickness Optimization ◽  
Wafer Level ◽  
Passivation Layers ◽  
Solder Balls ◽  
Interaction Stress ◽  
Underfill Material

Abstract Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material. The flat passivation design can reduce the chip package interaction for underfill material but it needed to be evaluated numerically for wafer level stress before being touted as a solution towards reducing passivation cracks. In Part II of this series of papers, the flat passivation layer thicknesses were numerically simulated and modified using response surface methodology design of experiments (RSM DOE) techniques. The optimized passivation layer thickness showed decreased stress which was validated using a simulation confirmation run.

Thermal Management in Direct Chip Attach Assemblies

1999 ◽  
Vol 121 (4) ◽  
pp. 222-230
Author(s):  
D. F. Baldwin ◽  
J. T. Beerensson
Keyword(s):  
Thermal Management ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Consumer Electronics ◽  
Thermal Design ◽  
Circuit Board ◽  
Thermal Dissipation ◽  
Experimental Measurements ◽  
Organic Substrates

Direct chip attach (DCA) packaging technologies are finding increasing application in electronics manufacturing particularly in telecommunications and consumer electronics. In these systems, bare die are interconnected directly to a printed circuit board. The two primary forms of DCA included chip on board (COB) where the die are attached face up and wirebonded to the substrate and flip chip on board (FCOB) where bumped die are interconnected active face down directly to low-cost organic substrates. In the current work, thermal management of four direct chip attach technologies is investigated. Experimental measurements are conducted exploring the junction-to-ambient thermal resistance and thermal dissipation paths for COB interconnection and three FCOB interconnect technologies including solder attach, anisotropic adhesive attach, and isotropic adhesive attach. A first-order chip-scale thermal design model is developed for flip chip assemblies exhibiting good agreement with the experimental measurements.

scholarly journals Sporadic Early Life Solder Ball Detachment Effects on Subsequent Microstructure Evolution and Fatigue of Solder Joints in Wafer-Level Chip-Scale Packages

2020 ◽  
Vol 17 (1) ◽  
pp. 13-22
Author(s):  
Simon Schambeck ◽  
Matthias Hutter ◽  
Johannes Jaeschke ◽  
Andrea Deutinger ◽  
Martin Schneider-Ramelow
Keyword(s):  
Thermal Loading ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Automotive Electronics ◽  
Wafer Level ◽  
Aging Effects ◽  
Chip Scale Package ◽  
Solder Balls

Abstract The combination of continuous miniaturization of electronics and the demanding reliability requirements for industrial and automotive electronics is one big challenge for emerging packaging technology. One aspect is to increase the understanding of the damage under environmental loading. Therefore, the solder joints of a wafer-level chip-scale package assembled on a printed circuit board (PCB) have been analyzed after a temperature cycling test. In the case of the investigated package, a limited number of joints did not form a proper mechanical connection with the PCB copper pad. Although not intended in the first place, these circumstances cause a detachment of those joints within the first few thermal cycles. However, this constellation offers a unique opportunity to compare the solder joint microstructure after thermomechanical loading (connected joints) with pure thermal loading (detached joints) located directly next to each other. It is shown that microstructure aging effects can be directly linked to regions in the joint with increased loading. This is particularly the case for detached joints, which could almost retain their initial microstructure up to the effect of the high-temperature part of the thermal profile. By means of finite element simulation, it is further possible to quantify the increased loading on adjacent joints if isolated solder balls detach from the board. In one case presented, the lifetime of the corner joint was calculated to reduce up to 85% only.

Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging

2018 ◽  
Vol 140 (1) ◽  
Author(s):  
Lei Shi ◽  
Lin Chen ◽  
David Wei Zhang ◽  
Evan Liu ◽  
Qiang Liu ◽  
...  
Keyword(s):  
Finite Element ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Coefficient Of Thermal Expansion ◽  
Equivalent Stress ◽  
Circuit Board ◽  
Electrical Performance ◽  
Design Parameters ◽  
Wafer Level ◽  
Element Analysis

Due to low cost and good electrical performance, wafer-level chip scale packaging (WLCSP) has gained more attention in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatches between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder–post interface where cracks were initiated and enlarges the intermetallic compounds (IMC) joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional (3D) finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P, the proposed WLCSP-PN reduces the package displacement, equivalent stress, and plastic strain energy density and thus improves the fatigue life of solder joints.

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