Reduction of Thermal Stress - Part II: Passivation Thickness Optimization of FLATPV Surface Bump Design

2017 ◽  
Vol 2017 (1) ◽  
pp. 000508-000512
Author(s):  
Raj Sekar Sethu ◽  
Salil Hari Kulkarni ◽  
How Ung Ha ◽  
Kok Heng Soon
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Passivation Layer ◽  
Fracture Rate ◽  
Thickness Optimization ◽  
Wafer Level ◽  
Passivation Layers ◽  
Solder Balls ◽  
Interaction Stress ◽  
Underfill Material

Abstract Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material. The flat passivation design can reduce the chip package interaction for underfill material but it needed to be evaluated numerically for wafer level stress before being touted as a solution towards reducing passivation cracks. In Part II of this series of papers, the flat passivation layer thicknesses were numerically simulated and modified using response surface methodology design of experiments (RSM DOE) techniques. The optimized passivation layer thickness showed decreased stress which was validated using a simulation confirmation run.

Packaging and Assembly Challenges for 2.5D/3D Devices

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001161-001191 ◽  
Author(s):  
Gerald Beyer ◽  
Kenneth Rebibis ◽  
Arnita Podpod ◽  
Francisco Cadacio ◽  
Teng Wang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Mechanical Stability ◽  
Coefficient Of Thermal Expansion ◽  
Wafer Level ◽  
Large Area ◽  
Molding Process ◽  
Process Step ◽  
Joint Formation ◽  
Bonding Force ◽  
Underfill Material

The continuous development of 2.5D/3D packaging and stack assembly technologies has enabled different ways of producing advanced packages for the said devices. Advancement in D2D, D2W and W2W bonding have allowed these devices to be a step closer to being fully manufactured in volume. Thermo-compression bonding (TCB) process in combination with a pre-applied underfill material (WLUF/NUF) have been developed and investigated for assembling 2.5D and 3D devices with fine pitch (10μm - 40 μm) μbumps. This assembly step though developed, is not without challenges. There is a need to select the right underfill material based on its mechanical and chemical properties which could contribute to issues such as die warping, voiding and non-wetting of μbumps. These materials should also be able to withstand several thermal steps within the entire stack assembly process and is able to pass reliability testing. During the TCB process, bonding forces have a profound impact on the joint formation behavior on the μbumps. A low bonding force could produce a joint formation with a lot of underfill filler entrapment and an incomplete reaction of the solder. A higher bonding force leads to more solder squeezing-out, leaving a thin and completely reacted intermetallic compound (IMC) layer in the joints. The D2D, D2W and W2W assembled chips can then be packaged into a standard flip chip component using laminate BGA substrates. But even with this volume manufacturing process, the introduction of 2.5D/3D stack devices brings another set of challenges to an existing assembly infrastructure. Challenges such as the handling of the stacked devices, the CTE mismatches of an entirely new set of materials and the constant scaling in FC bump (Cu Pillar or C4) pitches in an existing infrastructure remain. The limitations of organic BGA packages in terms of CTE mismatches and costs gave rise to Fan-out Wafer Level Packages (FOWLP) or a technique also known as wafer reconstruction. However, there are certain tradeoffs particularly in the molding process step of fully D2W stacked or reconstructed 300 mm wafers. Molding such a large area of stacked chips with very narrow gaps of around 50μm to 300μm is a major challenge especially in trying to maintain the flatness of the wafer for succeeding wafer level processing steps. The large warpage of over molded (D2W or reconstructed) wafers is due to the coefficient of thermal expansion (CTE) mismatch between silicon and the reconstruction material. Therefore careful selection of materials and design of reconstructed structures is needed. Other techniques to keep the D2W or reconstructed assemblies are being developed and evaluated. Also by selecting an FOWLP or reconstructed wafer type of package, the integration of temporary bonding materials (TBMs) in TCB and wafer molding becomes a challenge. In order to produce the reconstructed wafer or the thinned D2W assembly, thermal and mechanical stability is required for such a material. In summary, the combination of advance stacking techniques and materials within certain 2.5D/3D integration flows could produce a low-cost and reliable 3D package. But these combinations will pose a number of challenges that needs to be addressed. This paper will discuss the different integration flows, stacking and packaging assembly techniques (and their challenges) that could make volume manufacturing possible for 2.5D/3D devices in the future.

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)

2011 ◽  
Author(s):  
Pushkraj Tumne ◽  
Vikram Venkatadri ◽  
Santosh Kudtarkar ◽  
Michael Delaus ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Flip Chip ◽  
Bulk Solder ◽  
Consumer Electronics ◽  
Drop Test ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Wafer Level ◽  
Cross Sectional ◽  
Right Censored Data ◽  
Solder Balls

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

Design and fabrication of MEMS-type compliant overhang flip-chip interconnect for RF applications

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 002082-002094
Author(s):  
Pingye Xu ◽  
Michael C. Hamilton
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Organic Substrate ◽  
Process Temperature ◽  
High Yield ◽  
Wafer Level ◽  
Micro Fabrication ◽  
Compliant Interconnect ◽  
Sac Solder

With the increase of I/O density and scaling of interconnects, conventional solder ball interconnects are required to be made smaller. As a result, the reliability of the conventional solder ball flip-chip interconnects worsens. One method to mitigate this issue is by using underfill. However, underfill undermines the reworkability of the solder joints and is challenging to apply when the gap between chip and substrate is small. Another approach to enhance the reliability is to use taller solder ball interconnects, which is however usually more costly. Instead of using conventional solder ball interconnects, compliant interconnects have also been researched in the past few decades to mitigate the reliability issue. The use of compliant structures can compensate for the coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic substrate. In this work, we present the design and fabrication of MEMS-type compliant overhang flip-chip interconnects. The structures are placed at the end of a coplanar waveguide (CPW) as interconnects between CPWs to research their performance at radio frequency (RF). A micro-fabrication process was adopted to build the interconnects. The CPWs are fabricated using conventional e-beam deposition followed by photolithography and then copper electroplating. The compliant overhangs were fabricated on top of a dome of reflowed photoresist on the CPWs to form a curved shape. The reflow and hard bake of the photoresist requires a process temperature of above 220 °C, which is similar to the reflow temperature of a Sn-Ag-Cu (SAC) solder. Therefore we believe our process is compatible with SAC solder processing infrastructures in terms of process temperature. The fabricated structures show high yield and uniformity. Due to the use of a micro-fabrication based process, the structures have the potential to be scaled and be compatible to wafer level packaging. The CPWs were then flip-chip bonded with the compliant interconnect as transitions. The RF performance of the interconnects up to 50 GHz will be presented.

Multi-Stacked Flip Chips with Copper Plated Through Silicon Vias and Re-distribution for 3D System-in-Package Integration

2006 ◽  
Vol 970 ◽  
Author(s):  
Shi-Wei Ricky Lee ◽  
Ronald Hon
Keyword(s):  
Flip Chip ◽  
Three Dimensional ◽  
Back Side ◽  
Wafer Level ◽  
Flip Chips ◽  
Electrical Interconnection ◽  
Solder Balls ◽  
Original Size ◽  
Structure Lead ◽  
Silicon Vias

ABSTRACTThe study is a prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs for interconnection. Three chips are stacked together to make a 3DP with solder bumped flip chips. TSVs are fabricated and distributed along the periphery of the middle chip. The TSVs are formed by dry etching, deep reactive ions etching (DRIE), with dimensions of 150 × 100 microns. The TSVs are plugged by copper plating. The filled TSVs are connected to the solder pads by extended pad patterns surrounding the top and the bottom of TSVs on both sides of the wafer for the middle chip. After pad patterning passivation and solder bumping, the wafer is sawed into chips for subsequent 3D stacked die assembly. Because the TSVs are located at the periphery of the middle chips and stretch across the saw street between adjacent chips, they will be sawed through their center to form two open TSVs (with half of the original size) for electrical interconnection between the front side and the back side of the middle chip. The top chip is made by the conventional solder bumped flip chip processes and the bottom chip is a carrier with some routing patterns. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented.

Interface Adhesion and Reliability of Microsystem Packaging

2003 ◽  
Vol 782 ◽  
Author(s):  
Marvin I. Francis ◽  
Kellen Wadach ◽  
Satyajit Walwadkar ◽  
Junghyun Cho
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Dissimilar Materials ◽  
Strain Energy Release ◽  
Interface Adhesion ◽  
Curing Conditions ◽  
Chip Technology ◽  
Solder Balls ◽  
Cte Mismatch

ABSTRACTFlip-chip technology is becoming one of the most promising packaging techniques for high performance packages. Solder balls are used as the connection technique in the flip-chip method and the connections are reinforced by filling in the spacing between the chip and substrate with underfill. The function of the underfill is to reduce the stresses in the solder joints caused by a coefficient of thermal expansion (CTE) mismatch. The presence of polymeric underfill material will, however, make the flip-chip packaging system susceptible to interfacial failure. Thus, the purpose of this study is to examine the interfacial delamination between the dissimilar materials in order to increase the reliability of the flip-chip interconnection method, and to understand the effect of underfill curing conditions on the interface adhesion. In particular, we use a linear elastic fracture mechanics (LEFM) approach to assess interfacial toughness. For this purpose, four-point bending testing is performed to determine a critical strain energy release rate, Gc. In addition, nano-indentation testing equipped with atomic force microscope (AFM) is employed to determine structure and properties of the underfill layer.

Reduction of Thermal Stress - Part III: UBM and Passivation Thickness Optimization

2017 ◽  
Vol 2017 (1) ◽  
pp. 000694-000698
Author(s):  
Raj Sekar Sethu ◽  
Salil Hari Kulkarni ◽  
How Ung Ha ◽  
Kok Heng Soon
Keyword(s):  
Finite Element Analysis ◽  
Solder Ball ◽  
Coefficient Of Thermal Expansion ◽  
Thickness Optimization ◽  
Wafer Level ◽  
Element Analysis ◽  
Wafer Level Packaging ◽  
Two Factors ◽  
Process Factors ◽  
Significant Factors

Abstract Integration of Back End Of Line (BEOL) CMOS technologies with Wafer Level Packaging (WLP) is challenging, as mismatch of Coefficient of Thermal Expansion (CTE) between materials can result in thermo-mechanical induced cracking. This is especially true during reflow cooling of wafers after the solder ball attach process. Factors that contribute towards cracking can be from both the BEOL as well the WLP process steps. Finite Element Analysis (FEA) of such designs can help identify possible root causes early in the design process and i.e. before actual fabrication. This would help save valuable prototyping & testing costs. In Part III of this series of FEA studies, two factors i.e. silicon nitride thickness (from the BEOL process), and the Under Bump Metalization (UBM) thickness (from the WLP process) were identified as significant factors in changing the maximum first principal stress levels in the passivation layer.

Warpage Analysis of Wafers With Film Coating

2001 ◽  
Author(s):  
Hai Ding ◽  
I. Charles Ume ◽  
Cheng Zhang
Keyword(s):  
Young’S Modulus ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Young's Modulus ◽  
Film Coating ◽  
Wafer Level ◽  
Element Analysis ◽  
Low Temperature Storage ◽  
Shadow Moire ◽  
Shadow Moiré

Abstract Wafer-level packaging (WLP) is one of the trends of electronic packaging in the 21st century. Since 1994, many companies have released WLP licenses. One of the common concerns among these various approaches is wafer warpage. Warpage of wafer tends to introduces crack or delamination during dicing and low temperature storage process. After wafer dicing, warpage could reduce the quality of each package in the long run. Many documented works indicated that in the design and implementation of WLP, some key parameters have to be carefully considered and closely controlled to ensure higher packaging quality with the minimum warpage. For the case of wafer-level flip chip, the key parameters are Young’s modulus, thickness, and coefficient of thermal expansion (CTE) of underfill. In this research, an experimental design and statistical methods have been used to identify the model structure and parameters that are critical to the warpage of wafers. Regression models were identified based on the data obtained from finite element analysis (FEA) that is verified by shadow Moiré experiments. According to the models, the CTE, the coupling of Young’s modulus and CTE, and the coupling of thickness and CTE of underfill primarily determine wafer warpage. Further FEA and shadow Moiré experiments indicate that the models are capable of predicting of wafer warpage in the process of WLP.

Development of No Flow Underfills for Lead-Free Flip Chip Applications

2006 ◽  
Author(s):  
Kaustubh Nagarkar ◽  
Tan Zhang ◽  
David Esler ◽  
David Simon ◽  
Paul Gillespie ◽  
...  
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Stencil Printing ◽  
Significant Research ◽  
Flip Chip Packaging ◽  
Chip Carrier ◽  
Packaging Industry ◽  
The Impact ◽  
Semiconductor Packaging ◽  
Underfill Material

Flip chip packaging is one of the fastest growing segments in electronics packaging technology. The semiconductor packaging industry is continuing to migrate towards Pb-free electronics assembly. Therefore, the development of compatible materials for Pb-free flip chip packaging is critical to this transition [1]. Flip chip devices are commonly underfilled to compensate for the mismatch in the Coefficient of Thermal Expansion (CTE) between the die and the chip carrier. The No Flow Underfill (NFU) process is a type that can increase the throughput of the flip chip assembly process and reduce manufacturing costs. Significant research has been performed to develop NFUs for eutectic applications. However, further research is required for the development of NFUs that are compatible with the Pb-free solders and the high temperature reflow process associated with these solders. In this paper, the challenges associated with the development of 'filled' underfill formulations for assembly with the 95.5Sn/3.8Ag/0.7Cu bumped flip chip devices are discussed. The effects of process variables that affect voiding in the underfill layer have been presented. The impact on voiding due to stencil printing of the underfill has been discussed. The impact on assembly reliability due to the underfill material properties has also been reported.

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