SMALL-SCALE InGaP/GaAs HETEROJUNCTION BIPOLAR TRANSISTORS FOR HIGH-SPEED AND LOW-POWER INTEGRATED-CIRCUIT APPLICATIONS

2001 ◽  
Vol 11 (01) ◽  
pp. 115-136 ◽  
Author(s):  
TOHRU OKA ◽  
KOJI HIRATA ◽  
HIDEYUKI SUZUKI ◽  
KIYOSHI OUCHI ◽  
HIROYUKI UCHIYAMA ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Bipolar Transistors ◽  
Small Scale ◽  
Flip Flop ◽  
Base Electrode ◽  
Power Integrated Circuit

Small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) with high-speed as well as low-current operation are demonstrated. To reduce the emitter size SE and the base-collector capacitance CBC simultaneously, the HBTs are fabricated by using WSi/Ti as the base electrode and by burying SiO 2 in the extrinsic collector region. WSi/Ti metals simplify and facilitate processing to fabricate small base electrodes, and the buried SiO 2 reduces the parasitic CBC under the base electrode. The cutoff frequency fT of 156 GHz and the maximum oscillation frequency f max of 255 GHz were obtained at a collector current Ic of 3.5 mA for the HBT with SE of 0.5 μ m ×4.5 μ m , and fT of 114 GHz and f max of 230 GHz were obtained at IC of 0.9 mA for the HBT with SE of 0.25 μ m ×1.5 μ m . A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB·Ω with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed. low power integrated circuit applications.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals Subthreshold Region based Linear Feedback Shift Register

2019 ◽  
Vol 8 (6S2) ◽  
pp. 817-821
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
System Level ◽  
Linear Feedback ◽  
Portable Devices ◽  
Subthreshold Region ◽  
Flip Flop ◽  
Ultra Low Power

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

High-speed InGaP/GaAs heterojunction bipolar transistors with buried SiO2 using WSi as the base electrode

1997 ◽  
Vol 18 (4) ◽  
pp. 154-156 ◽  
Author(s):  
T. Oka ◽  
K. Ouchi ◽  
H. Uchiyama ◽  
T. Taniguchi ◽  
K. Mochizuki ◽  
...  
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
High Speed ◽  
Bipolar Transistors ◽  
Base Electrode

scholarly journals Design and analysis of Low Power High Speed Pulse Triggered Flip Flop

2016 ◽  
Vol 5 (03) ◽  
pp. 01-06
Author(s):  
Mr. Kankan Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
The Other ◽  
Discharge Time ◽  
Flip Flop ◽  
Power Pulse

The main important aspect is to outline a high speed and utilization of low power pulse triggered flip-flop and simulate the same. Also, we have to minimize leakage in the consumption of power in a flip-flop by employing pulse triggering technique that is adopted for clocks. Here, to solve the problem in the discharging path of the similar flip flop implementations, we employ signal feed through technique. The discharge time is reduced by the proposed method. This design out performs all the other similar pulse triggered flip flop implementation both in speed and power consumption. Now, it is implemented by employing Cadence Virtuoso Schematic Composer in 90nm GPDK. Simulation is done by a simulator known as Spectre.

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

1996 ◽  
Vol 31 (9) ◽  
pp. 1361-1363 ◽  
Author(s):  
T. Maeda ◽  
K. Numata ◽  
M. Fujii ◽  
M. Tokushima ◽  
S. Wada ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Low Power Consumption ◽  
Flip Flop ◽  
Ultra Low Power
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