scholarly journals Design and analysis of Low Power High Speed Pulse Triggered Flip Flop

2016 ◽  
Vol 5 (03) ◽  
pp. 01-06
Author(s):  
Mr. Kankan Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
The Other ◽  
Discharge Time ◽  
Flip Flop ◽  
Power Pulse

The main important aspect is to outline a high speed and utilization of low power pulse triggered flip-flop and simulate the same. Also, we have to minimize leakage in the consumption of power in a flip-flop by employing pulse triggering technique that is adopted for clocks. Here, to solve the problem in the discharging path of the similar flip flop implementations, we employ signal feed through technique. The discharge time is reduced by the proposed method. This design out performs all the other similar pulse triggered flip flop implementation both in speed and power consumption. Now, it is implemented by employing Cadence Virtuoso Schematic Composer in 90nm GPDK. Simulation is done by a simulator known as Spectre.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals Subthreshold Region based Linear Feedback Shift Register

2019 ◽  
Vol 8 (6S2) ◽  
pp. 817-821
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
System Level ◽  
Linear Feedback ◽  
Portable Devices ◽  
Subthreshold Region ◽  
Flip Flop ◽  
Ultra Low Power

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

SMALL-SCALE InGaP/GaAs HETEROJUNCTION BIPOLAR TRANSISTORS FOR HIGH-SPEED AND LOW-POWER INTEGRATED-CIRCUIT APPLICATIONS

2001 ◽  
Vol 11 (01) ◽  
pp. 115-136 ◽  
Author(s):  
TOHRU OKA ◽  
KOJI HIRATA ◽  
HIDEYUKI SUZUKI ◽  
KIYOSHI OUCHI ◽  
HIROYUKI UCHIYAMA ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Bipolar Transistors ◽  
Small Scale ◽  
Flip Flop ◽  
Base Electrode ◽  
Power Integrated Circuit

Small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) with high-speed as well as low-current operation are demonstrated. To reduce the emitter size SE and the base-collector capacitance CBC simultaneously, the HBTs are fabricated by using WSi/Ti as the base electrode and by burying SiO 2 in the extrinsic collector region. WSi/Ti metals simplify and facilitate processing to fabricate small base electrodes, and the buried SiO 2 reduces the parasitic CBC under the base electrode. The cutoff frequency fT of 156 GHz and the maximum oscillation frequency f max of 255 GHz were obtained at a collector current Ic of 3.5 mA for the HBT with SE of 0.5 μ m ×4.5 μ m , and fT of 114 GHz and f max of 230 GHz were obtained at IC of 0.9 mA for the HBT with SE of 0.25 μ m ×1.5 μ m . A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB·Ω with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed. low power integrated circuit applications.

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

1996 ◽  
Vol 31 (9) ◽  
pp. 1361-1363 ◽  
Author(s):  
T. Maeda ◽  
K. Numata ◽  
M. Fujii ◽  
M. Tokushima ◽  
S. Wada ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Low Power Consumption ◽  
Flip Flop ◽  
Ultra Low Power

New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption

2015 ◽  
Vol 24 (10) ◽  
pp. 1550159 ◽  
Author(s):  
Ramin Razmdideh ◽  
Ali Mahani ◽  
Mohsen Saneei
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Switching Activity ◽  
Flip Flop ◽  
Reduce Power Consumption ◽  
Controlled Switching ◽  
Simulation Results

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

scholarly journals DESIGN AND ANALYSIS OF LOW-POWER, HIGH-SPEED BAUGH WOOLEY MULTIPLIER

2019 ◽  
Vol 2019 (02) ◽  
pp. 60-70
Author(s):  
Karuppusamy P
Keyword(s):  
Performance Analysis ◽  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Paper Analysis ◽  
The Other ◽  
Very High

The fundamental operations of the communication are the multiplication and division. The multiplier usually consumes a larger area and power and poses a very high latency. As all the above mentioned characteristics of the multiplier depends on the techniques utilized for the multiplication. It becomes necessary to put into effect a proper multiplier that reduces both the latency and the power consumption. So the paper analysis the performance of the various multipliers and scopes to develop a low power high speed multiplier based on the Baugh Wooley algorithm. The Performance analysis of the Baugh Wooley multiplier and the other existing multipliers is done and was found that the performance of the Baugh Wooley in terms of the latency and the power consumption was convincing compared to the other existing methods.

scholarly journals AREA AND POWER OPTIMIZED D-FLIP FLOP AND SUBTRACTOR

2021 ◽  
Vol 9 (1) ◽  
pp. 159-163
Author(s):  
T. Subhashini, M. Kamaraju, K. Babulu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Modern Technology ◽  
Power Reduction ◽  
Flip Flop ◽  
Xor Gate ◽  
Long Run

Low power is essential in today’s technology. It is most significant with high speed, small size and stability. So, power reduction is most important in modern technology using VLSI design techniques. Today most of the market necessities require low power, long run time and market which also deserve small size and high speed. In this paper several logic circuits DFF with 5 transistors and sub tractor circuit using powerless XOR gate and Groundless XNOR gates are implemented. In the proposed DFF, the area can be decreased by 62% & substarctor circuit, area decreased by 80% and power consumption of DFF and subtractor circuit are 15.4µW and 13.76µW respectively, but these are very less as compared to existing techniques.  

scholarly journals DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY

2013 ◽  
pp. 260-264
Author(s):  
B. FRANCIS ◽  
Y. APPARAO ◽  
B. CHINNARAO
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Short Pulse ◽  
Propagation Delay ◽  
Deep Submicron ◽  
Leakage Power ◽  
Flip Flop ◽  
Propagation Delays

This paper enumerates low power, high speed design of flip-flop having less number of transistors and only one transistor being clocked by short pulse train which is true single phase clocking (TSPC) flip-flop. Compared to Conventional flip-flop, it has 5 Transistors and one transistor clocked, thus has lesser size and lesser power consumption. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The analysis for various flip flops and latches for power dissipation and propagation delays at 0.13μm and 0.35μm technologies is carried out. The leakage power increases as technology is scaled down. The leakage power is reduced by using best technique among all run time techniques viz. MTCMOS. Thereby comparison of different conventional flip-flops, latches and TSPC flip-flop in terms of power consumption, propagation delays and product of power dissipation and propagation delay with SPICE simulation results is presented.

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