2 KV 4H-SiC DMOSFETS FOR LOW LOSS, HIGH FREQUENCY SWITCHING APPLICATIONS

2004 ◽  
Vol 14 (03) ◽  
pp. 879-883 ◽  
Author(s):  
SEI-HYUNG RYU ◽  
SUMI KRISHNASWAMI ◽  
MRINAL DAS ◽  
JAMES RICHMOND ◽  
ANANT ANANT AGARWAL ◽  
...  

Due to the high critical field in 4 H - SiC , the drain charge and switching loss densities in a SiC power device are approximately 10X higher than that of a silicon device. However, for the same voltage and resistance ratings, the device area is much smaller for the 4 H - SiC device. Therefore, the total drain charge and switching losses are much lower for the 4 H - SiC power device. A 2.3 kV, 13.5 mΩ-cm2 4 H - SiC power DMOSFET with a device area of 2.1 mm × 2.1 mm has been demonstrated. The device showed a stable avalanche at a drain bias of 2.3 kV, and an on-current of 5 A with a VGS of 20 V and a VDS of 2.6 V. Approximately an order of magnitude lower parasitic capacitance values, as compared to those of commercially available silicon power MOSFETs, were measured for the 4 H - SiC power DMOSFET. This suggests that the 4 H - SiC DMOSFET can provide an order of magnitude improvement in switching performance in high speed switching applications.

2005 ◽  
Vol 483-485 ◽  
pp. 797-800 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Sumi Krishnaswami ◽  
Mrinal K. Das ◽  
Jim Richmond ◽  
Anant K. Agarwal ◽  
...  

Due to the high critical field in 4H-SiC, the drain charge and switching loss densities in a SiC power device are approximately 10X higher than that of a silicon device. However, for the same voltage and resistance ratings, the device area is much smaller for the 4H-SiC device. Therefore, the total drain charge and switching losses are much lower for the 4H-SiC power device. A 2.3 kV, 13.5 mW-cm2 4H-SiC power DMOSFET with a device area of 2.1 mm x 2.1 mm has been demonstrated. The device showed a stable avalanche at a drain bias of 2.3 kV, and an on-current of 5 A with a VGS of 20 V and a VDS of 2.6 V. Approximately an order of magnitude lower parasitic capacitance values, as compared to those of commercially available silicon power MOSFETs, were measured for the 4H-SiC power DMOSFET. This suggests that the 4H-SiC DMOSFET can provide an order of magnitude improvement in switching performance in high speed switching applications.


2019 ◽  
Vol 963 ◽  
pp. 596-599
Author(s):  
Shuhei Nakata ◽  
Shota Tanaka

Recentlly, high speed switching circuits using SiC power device have been developed for reduction of switching loss and downsizing of electric products. The high speed switching leads to the rapid changing of the drain voltage (dV/dt) during the switching period. This paper reports the effects of the dV/dt impact on the self-turn-on and the characteristics of SiC-MOSFET, especially the temperature dependence. The results shows that the gate bias voltage to suppress the self-turn-on is negatively correlated with the temperature. And it is also found that the dV/dt impact breaks down the gate source insulation and the dV/dt value to the breakdown is positively correlated with the temperature.


2019 ◽  
Vol 963 ◽  
pp. 797-800 ◽  
Author(s):  
Ajit Kanale ◽  
Ki Jeong Han ◽  
B. Jayant Baliga ◽  
Subhashish Bhattacharya

The high-temperature switching performance of a 1.2kV SiC JBSFET is compared with a 1.2kV SiC MOSFET using a clamped inductive load switching circuit representing typical H-bridge inverters. The switching losses of the SiC MOSFET are also evaluated with a SiC JBS Diode connected antiparallel to it. Measurements are made with different high-side and low-side device options across a range of case temperatures. The JBSFET is observed to display a reduction in peak turn-on current – up to 18.9% at 150°C and a significantly lesser turn-on switching loss – up to 46.6% at 150°C, compared to the SiC MOSFET.


2012 ◽  
Vol 717-720 ◽  
pp. 1097-1100 ◽  
Author(s):  
Shiro Hino ◽  
Naruhisa Miura ◽  
Akihiko Furukawa ◽  
Shoyu Watanabe ◽  
Yukiyasu Nakao ◽  
...  

High speed switching is desired to reduce switching losses of SiC-MOSFETs. In order to realize SiC-MOSFETs capable of high speed switching, we numerically evaluated the electric field induced in SiC-MOSFETs during switching using an equivalent circuit model. Based on the evaluation, we designed a SiC-MOSFET, which successfully demonstrated high speed switching with a dV/dt of over 70 V/ns.


2019 ◽  
Vol 963 ◽  
pp. 625-628
Author(s):  
Ajit Kanale ◽  
B. Jayant Baliga ◽  
Ki Jeong Han ◽  
Subhashish Bhattacharya

The high-temperature switching performance of a 1.2kV SiC JBSFET is compared with a 1.2kV SiC MOSFET using a clamped inductive load switching circuit representing typical H-bridge inverters. The switching losses of the SiC MOSFET are also evaluated with a SiC JBS Diode connected antiparallel to it. Measurements are made with different high-side and low-side device options across a range of case temperatures. The JBSFET is observed to display a reduction in peak turn-on current – up to 18.9% at 150°C and a significantly lesser turn-on switching loss – up to 46.6% at 150°C, compared to the SiC MOSFET.


2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Sibylle Dieckerhoff ◽  
Thies Wernicke ◽  
Christine Kallmayer ◽  
Stephan Guttowski ◽  
Herbert Reichl

The impact of a reduced package stray inductance on the switching performance of fast power MOSFETs is discussed applying advanced 3D packaging technologies. Starting from an overview over new packaging approaches, a solder bump technology using a flexible PI substrate is exemplarily chosen for the evaluation. Measurement techniques to determine the stray inductance are discussed and compared with a numerical solution based on the PEEC method. Experimental results show the improvement of the voltage utilization while there is only a slight impact on total switching losses.


1982 ◽  
Vol 29 (6) ◽  
pp. 1555-1558 ◽  
Author(s):  
D. L. Blackburn ◽  
D. W. Berning ◽  
J. M. Benedetto ◽  
K. F. Galloway

2018 ◽  
Vol 924 ◽  
pp. 756-760 ◽  
Author(s):  
Xue Qing Liu ◽  
Sauvik Chowdhury ◽  
Collin W. Hitchcock ◽  
T. Paul Chow

1200V SiC power MOSFETs of various cell geometries are modeled in Synopsis Inc. Sentaurus TCAD. The impact of cell geometry on switching loss is studied by comparing the turn-on and turn-off losses using refined calculation methods. Under optimum circuit conditions, two different novel unit cell designs each achieve lower switching losses than conventional designs. For all the designs, lossless turn-on is impossible but lossless turn-off is achievable under circuit and biasing conditions that produce sufficiently rapid gate slew.


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