Experimental Study of High-Temperature Switching Performance of 1.2kV SiC JBSFET in Comparison with 1.2kV SiC MOSFET

2019 ◽  
Vol 963 ◽  
pp. 625-628
Author(s):  
Ajit Kanale ◽  
B. Jayant Baliga ◽  
Ki Jeong Han ◽  
Subhashish Bhattacharya

The high-temperature switching performance of a 1.2kV SiC JBSFET is compared with a 1.2kV SiC MOSFET using a clamped inductive load switching circuit representing typical H-bridge inverters. The switching losses of the SiC MOSFET are also evaluated with a SiC JBS Diode connected antiparallel to it. Measurements are made with different high-side and low-side device options across a range of case temperatures. The JBSFET is observed to display a reduction in peak turn-on current – up to 18.9% at 150°C and a significantly lesser turn-on switching loss – up to 46.6% at 150°C, compared to the SiC MOSFET.

2019 ◽  
Vol 963 ◽  
pp. 797-800 ◽  
Author(s):  
Ajit Kanale ◽  
Ki Jeong Han ◽  
B. Jayant Baliga ◽  
Subhashish Bhattacharya

The high-temperature switching performance of a 1.2kV SiC JBSFET is compared with a 1.2kV SiC MOSFET using a clamped inductive load switching circuit representing typical H-bridge inverters. The switching losses of the SiC MOSFET are also evaluated with a SiC JBS Diode connected antiparallel to it. Measurements are made with different high-side and low-side device options across a range of case temperatures. The JBSFET is observed to display a reduction in peak turn-on current – up to 18.9% at 150°C and a significantly lesser turn-on switching loss – up to 46.6% at 150°C, compared to the SiC MOSFET.


2016 ◽  
Vol 858 ◽  
pp. 885-888 ◽  
Author(s):  
Yuichiro Nanen ◽  
Masatoshi Aketa ◽  
Yuki Nakano ◽  
Hirokazu Asahara ◽  
Takashi Nakamura

Dynamic and static characteristics of SiC power MOSFETs at high temperature up to 380°C were investigated. Investigated devices have exhibited a behavior as a normally-off MOSFET even at such high temperature as 380°C. Temperature dependence of the MOSFET characteristics are reported in this paper, such as threshold voltage (VTH), on-resistance, internal gate resistance, and turn-on and turn-off losses (EON, EOFF). EON decreases and EOFF increases with increased temperature. Temperature dependence of switching losses is affected by transfer time of VDS, which was mainly determined from VTH.


2008 ◽  
Vol 600-603 ◽  
pp. 1067-1070 ◽  
Author(s):  
Rajesh Kumar Malhan ◽  
S.J. Rashid ◽  
Mitsuhiro Kataoka ◽  
Yuuichi Takeuchi ◽  
Naohiro Sugiyama ◽  
...  

Static and dynamic behavior of the epitaxially grown dual gate trench 4H-SiC junction field effect transistor (JFET) is investigated. Typical on-state resistance Ron was 6 – 10mΩcm2 at VGS = 2.5V and the breakdown voltage between the range of 1.5 – 1.8kV was realized at VGS = −5V for normally-off like JFETs. It was found that the turn-on energy delivers the biggest part of the switching losses. The dependence of switching losses from gate resistor is nearly linear, suggesting that changing the gate resistor, a way similar to Si-IGBT technology, can easily control di/dt and dv/dt. Turn-on losses at 200°C are lower compared to those at 25°C, which indicates the influence of the high internal p-type gate layer resistance. Inductive switching numerical analysis suggested the strong influence of channel doping conditions on the turn-on switching performance. The fast switching normally-off JFET devices require heavily doped narrow JFET channel design.


2004 ◽  
Vol 14 (03) ◽  
pp. 879-883 ◽  
Author(s):  
SEI-HYUNG RYU ◽  
SUMI KRISHNASWAMI ◽  
MRINAL DAS ◽  
JAMES RICHMOND ◽  
ANANT ANANT AGARWAL ◽  
...  

Due to the high critical field in 4 H - SiC , the drain charge and switching loss densities in a SiC power device are approximately 10X higher than that of a silicon device. However, for the same voltage and resistance ratings, the device area is much smaller for the 4 H - SiC device. Therefore, the total drain charge and switching losses are much lower for the 4 H - SiC power device. A 2.3 kV, 13.5 mΩ-cm2 4 H - SiC power DMOSFET with a device area of 2.1 mm × 2.1 mm has been demonstrated. The device showed a stable avalanche at a drain bias of 2.3 kV, and an on-current of 5 A with a VGS of 20 V and a VDS of 2.6 V. Approximately an order of magnitude lower parasitic capacitance values, as compared to those of commercially available silicon power MOSFETs, were measured for the 4 H - SiC power DMOSFET. This suggests that the 4 H - SiC DMOSFET can provide an order of magnitude improvement in switching performance in high speed switching applications.


2005 ◽  
Vol 483-485 ◽  
pp. 797-800 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Sumi Krishnaswami ◽  
Mrinal K. Das ◽  
Jim Richmond ◽  
Anant K. Agarwal ◽  
...  

Due to the high critical field in 4H-SiC, the drain charge and switching loss densities in a SiC power device are approximately 10X higher than that of a silicon device. However, for the same voltage and resistance ratings, the device area is much smaller for the 4H-SiC device. Therefore, the total drain charge and switching losses are much lower for the 4H-SiC power device. A 2.3 kV, 13.5 mW-cm2 4H-SiC power DMOSFET with a device area of 2.1 mm x 2.1 mm has been demonstrated. The device showed a stable avalanche at a drain bias of 2.3 kV, and an on-current of 5 A with a VGS of 20 V and a VDS of 2.6 V. Approximately an order of magnitude lower parasitic capacitance values, as compared to those of commercially available silicon power MOSFETs, were measured for the 4H-SiC power DMOSFET. This suggests that the 4H-SiC DMOSFET can provide an order of magnitude improvement in switching performance in high speed switching applications.


2018 ◽  
Vol 924 ◽  
pp. 756-760 ◽  
Author(s):  
Xue Qing Liu ◽  
Sauvik Chowdhury ◽  
Collin W. Hitchcock ◽  
T. Paul Chow

1200V SiC power MOSFETs of various cell geometries are modeled in Synopsis Inc. Sentaurus TCAD. The impact of cell geometry on switching loss is studied by comparing the turn-on and turn-off losses using refined calculation methods. Under optimum circuit conditions, two different novel unit cell designs each achieve lower switching losses than conventional designs. For all the designs, lossless turn-on is impossible but lossless turn-off is achievable under circuit and biasing conditions that produce sufficiently rapid gate slew.


2011 ◽  
Vol 679-680 ◽  
pp. 633-636 ◽  
Author(s):  
Brett A. Hull ◽  
Sei Hyung Ryu ◽  
Q. Jon Zhang ◽  
Charlotte Jonas ◽  
Michael J. O'Loughlin ◽  
...  

DMOSFETs fabricated in 4H-SiC with capabilities for blocking in excess of 1700V and conducting 20A continuous current in the on-state are presented. These SiC DMOSFETs remain functional to temperatures in excess of 225°C, with leakage current at 1700V at 225°C of less than 5 A with VGS = 0V. The DMOSFETs show excellent switching characteristics, with total switching energy of 1.8 to 1.95 mJ over the entire temperature range of testing (25°C to 200°C), when switched from the blocking state at 1200V to conducting at 20A in a clamped inductive load switching circuit. The electrical characteristics are compared to commercially available Si IGBTs rated to 1700V with similar current ratings as the SiC DMOSFET described herein.


2018 ◽  
Author(s):  
M. Wang ◽  
Q. Xiao ◽  
Y. Gou ◽  
F. Deng ◽  
B. Wang ◽  
...  

2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.


2021 ◽  
Vol 6 (24) ◽  
pp. 6286-6294
Author(s):  
Tahir Savran ◽  
Sukriye Nihan Karuk Elmas ◽  
Gonul Akin Geyik ◽  
Aykut Bostanci ◽  
Duygu Aydin ◽  
...  

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