LOW POWER ENERGY RECOVERY COMPLEMENTARY PASS-TRANSISTOR LOGIC

2006 ◽  
Vol 15 (04) ◽  
pp. 491-504
Author(s):  
ROBERT C. CHANG ◽  
PO-CHUNG HUNG ◽  
HSIN-LEI LIN
Keyword(s):  
Energy Recovery ◽  
Power Saving ◽  
Cmos Technology ◽  
Power Reduction ◽  
Two Phase ◽  
Look Ahead ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Pass Transistor Logic ◽  
Efficient Power

A proposed adiabatic logic called Energy Recovery Complementary Pass-transistor Logic (ERCPL) is presented in this paper. It operates with a two-phase nonoverlapping power-clock supply. It uses bootstrapping to achieve efficient power saving and eliminates any nonadiabatic losses on the charge-steering devices. A scheme is used to recover part of the energy trapped in the bootstrapping nodes. We compare the energy dissipation between ERCPL and other logic circuits by simulation. Simulation results show that a pipelined ERCPL carry look-ahead adder can achieve a power reduction of 80% over the conventional CMOS case. Operation of an 8-bit ERCPL CLA fabricated using the TSMC 0.35 μm 1P4M CMOS technology has been experimentally verified.

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)

2017 ◽  
Vol 27 (04) ◽  
pp. 1850052 ◽  
Author(s):  
P. Sasipriya ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Energy Efficiency ◽  
Low Power ◽  
Energy Recovery ◽  
Dynamic Logic ◽  
Vlsi Circuits ◽  
Clock Signal ◽  
Two Phase ◽  
Look Ahead ◽  
Adiabatic Logic ◽  
Speed Performance

This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180[Formula: see text]nm technology library files.

Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits

2017 ◽  
Vol 16 (3) ◽  
pp. 867-874 ◽  
Author(s):  
Ajay Kumar Dadoria ◽  
Kavita Khare ◽  
Tarun K. Gupta ◽  
Nilay Khare
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Pass Transistor ◽  
Pass Transistor Logic

Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction

2010 ◽  
Vol 159 ◽  
pp. 180-185 ◽  
Author(s):  
Jian Ping Hu ◽  
Yu Zhang
Keyword(s):  
Energy Savings ◽  
Cmos Process ◽  
Gate Length ◽  
Mos Transistors ◽  
Traffic Light ◽  
Leakage Currents ◽  
Two Phase ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
The One

Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. To decrease leakage power dissipations is becoming more and more important in low-power nanometer circuits. This paper proposes a gate-length biasing technique for complementary pass-transistor adiabatic logic (CPAL) circuits to reduce sub-threshold leakage dissipations. The flip-flops based on CPAL circuits with gate-length biasing techniques are presented. A traffic light controller using two-phase CPAL with gate-length biasing technique is demonstrated at 45nm CMOS process. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE. Simulation results show that the CPAL traffic light controller with the gate-length biasing technique attains 20% to 5% energy savings compared with the one using the original gate length 25MHz to 200MHz.

A LOW POWER 2.4 GHz RF TRANSCEIVER FOR ZIGBEE APPLICATIONS

2013 ◽  
Vol 22 (09) ◽  
pp. 1340007 ◽  
Author(s):  
WEIYANG LIU ◽  
JINGJING CHEN ◽  
HAIYONG WANG ◽  
NANJIAN WU
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Power Saving ◽  
Cmos Technology ◽  
Low Noise ◽  
Rf Transceiver ◽  
Power Efficient ◽  
Noise Amplifier ◽  
Low If Receiver ◽  
Efficient Power

This paper presents a low power RF transceiver for 2.4 GHz ZigBee applications. The current reused inductor-less-load balun low noise amplifier (LNA) with quadrature mixer is proposed for area and power saving for low-IF receiver. The transmitter adopts power efficient power amplifier (PA) to improve transmitting efficiency. This RF transceiver is implemented in 0.18 μm CMOS technology. The receiver achieves 6.5 dB noise figure (NF) and 20 dB conversion gain. The transmitter delivers maximum +3 dBm output power with PA efficiency of 30%. The receiver and transmitter front-end dissipate 1.9 mW and 5.3 mW at 1.8 V supply, respectively. The whole die area is 0.95 mm2.

Differential pass transistor logic in CMOS technology

1986 ◽  
Vol 22 (6) ◽  
pp. 294 ◽  
Author(s):  
A.S. Shubat ◽  
J.A. Pretorius ◽  
C.A.T. Salama
Keyword(s):  
Cmos Technology ◽  
Pass Transistor ◽  
Pass Transistor Logic

scholarly journals Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)

2018 ◽  
Vol 7 (3) ◽  
pp. 1548
Author(s):  
P Sasipriya ◽  
V S Kanchana Bhaaskaran
Keyword(s):  
Low Power ◽  
High Speed ◽  
Dynamic Logic ◽  
Logic Circuits ◽  
Clock Signal ◽  
Two Phase ◽  
Industry Standard ◽  
Look Ahead ◽  
Adiabatic Logic ◽  
Sequential Logic

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.  

Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library

2016 ◽  
Vol 833 ◽  
pp. 149-156
Author(s):  
L. Gurusamy ◽  
Muhammad Kashif ◽  
Norhuzaimin Julai
Keyword(s):  
Cmos Technology ◽  
Power Reduction ◽  
Improve Performance ◽  
Standard Cell Library ◽  
Prefix Tree ◽  
Cell Library ◽  
Look Ahead ◽  
Chip Size ◽  
Parallel Prefix ◽  
Prefix Adder

This This paper addresses a novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA). Ling’s algorithm is used to optimise the pre-processing blocks (white nodes) and intermediate Generate-Propagate blocks (Black nodes) of the prefix tree to minimise the congestion of wires which contributes to reduction in chip size and to improve performance. The resulting prefix-tree arrangement is then merged into a sequence of modified CSEA. Experimental results show that HPA has speed improvement of 62% and 13% power reduction in comparison of the traditional Carry Look-Ahead Adder (CLA).

scholarly journals Design and Implementation of Low Power Multiplier Using Proposed Two Phase Clocked Adiabatic Static CMOS Logic Circuit

2018 ◽  
Vol 8 (6) ◽  
pp. 4959
Author(s):  
Minal Keote ◽  
P. T. Karule
Keyword(s):  
Low Power ◽  
Energy Recovery ◽  
Power Reduction ◽  
Logic Circuit ◽  
Digital Systems ◽  
Two Phase ◽  
Measurement Result ◽  
Design And Implementation ◽  
Adiabatic Energy ◽  
Low Power Multiplier

<p class="Abstract">This paper presents a design and implementation of 2*2 array and 4*4 array multiplier using proposed Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed 2PASCL circuit is based on adiabatic energy recovery principle which consumes less power. The proposed 2PASCL uses two sinusoidal power clocks which are 1800 phase shifted with each other. The measurement result of 2*2 array proposed 2PASCL multiplier gives 80.16 % and 97.67 %power reduction relative to reported 2PASCL and conventional CMOS logic and the measurement result of 4*4 array proposed 2PASCL multiplier demonstrate 32.88 % and 82.02 %power reduction compared to reported 2PASCL and conventional CMOS logic . Another advantage of the proposed circuit is that it gives less power though the number of transistor in proposed and reported 2PASCL circuit is same. From the result we conclude that proposed 2PASCL technology is advantageous to application in low power digital systems, pacemakers and sensors. The circuits are simulated at 180nm technology mode.</p>

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