scholarly journals Different Types of Ultra-low Power Energy-Harvesting Design Techniques for IoT Applications

2019 ◽  
Vol 9 (1S5) ◽  
pp. 118-121
Keyword(s):  
Energy Harvesting ◽  
Power Consumption ◽  
Low Voltage ◽  
Threshold Level ◽  
Electronic Systems ◽  
Cmos Inverter ◽  
Switching Speed ◽  
Ultra Low Power ◽  
Level Shifter ◽  
Design Techniques

In this paper, different type of level shifter circuits, that can able to convert the sub-threshold level to superthreshold level signals are discussed. To develop the ultra- low static power consumption circuit designs such a way to switch on the transistor for a low voltage levels. To enhance the switching speed and minimize the dynamic power consumption, by incorporating the CMOS –inverter buffer circuit at the output side to improve the energy efficiently. These energy harvesting design techniques provides endless energy supply to electronic systems that are remotely located areas. More number of devices are controlled by IoT (Internet of Things) to perform the operation by remote sensing.

Ultra-Low Power, Low Voltage, Self-Powered Resonant DC–DC Converter for Energy Harvesting

2013 ◽  
Vol 9 (1) ◽  
pp. 103-117 ◽  
Author(s):  
Salah-Eddine Adami ◽  
Nicolas Degrenne ◽  
Walid Haboubi ◽  
Hakim Takhedmit ◽  
Denis Labrousse ◽  
...  
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Low Voltage ◽  
Ultra Low Power ◽  
Self Powered

Wireless Vibration Sensing Without a Battery

2012 ◽  
Author(s):  
Haiying Huang ◽  
Yayu Hew
Keyword(s):  
Energy Harvesting ◽  
Power Consumption ◽  
Low Power ◽  
Strain Gauge ◽  
Sensor Node ◽  
Wireless Sensor ◽  
Low Power Consumption ◽  
Wireless Sensor Node ◽  
Signal Modulation ◽  
Ultra Low Power

This paper presents the implementation and characterization of a low power wireless vibration sensor that can be powered by a flash light. The wireless system consists of two components, namely the wireless sensor node and the wireless interrogation unit. The wireless sensor node includes a wireless strain gauge that consumes around 6 mW, a signal modulation circuit, and a light energy harvesting unit. To achieve ultra-low power consumption, the signal modulation circuit was implemented using a voltage-controlled oscillator (VCO) to convert the strain gauge output to an intermediate frequency (IF) signal, which is then used to alter the impedance of the sensor antenna and thus achieves amplitude modulation of the backscattered antenna signal. A generic solar panel with energy harvesting circuit is used to power the strain sensor node continuously. The wireless interrogation unit transmits the interrogation signal and receives the amplitude modulated antenna backscattering, which can be down-converted to recover the IF signal. In order to measure the strains dynamically, a Phase Lock Loop (PLL) circuit was implemented at the interrogator to track the frequency of the IF signal and provide a signal that is directly proportional to the measured strain. The system features ultra-low power consumption, complete wireless sensing, solar powering, and portability. The application of this low power wireless strain system for vibration measurement is demonstrated and characterized.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

2020 ◽  
Vol 10 (4) ◽  
pp. 457-470 ◽  
Author(s):  
Dipanjan Sen ◽  
Savio J. Sengupta ◽  
Swarnil Roy ◽  
Manash Chanda ◽  
Subir K. Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Dominant Factor ◽  
Double Gate ◽  
Cmos Inverter ◽  
Ultra Low Power ◽  
Voltage Swing

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

scholarly journals Design Techniques for Low-Power and Low-Voltage Bandgaps

Electricity ◽  
2021 ◽  
Vol 2 (3) ◽  
pp. 271-284
Author(s):  
Edoardo Barteselli ◽  
Luca Sant ◽  
Richard Gaggl ◽  
Andrea Baschirotto
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Design Guidelines ◽  
The Other ◽  
Bandgap Reference ◽  
Operation Conditions ◽  
Error Amplifier ◽  
Thermal Voltage ◽  
Design Techniques

Reverse bandgaps generate PVT-independent reference voltages by means of the sums of pairs of currents over individual matched resistors: one (CTAT) current is proportional to VEB; the other one (PTAT) is proportional to VT (Thermal voltage). Design guidelines and techniques for a CMOS low-power reverse bandgap reference are presented and discussed in this paper. The paper explains firstly how to design the components of the bandgap branches to minimize circuit current. Secondly, error amplifier topologies are studied in order to reveal the best one, depending on the operation conditions. Finally, a low-voltage bandgap in 65 nm CMOS with 5 ppm/°C, with a DC PSR of −91 dB, with power consumption of 5.2 μW and with an area of 0.0352 mm2 developed with these techniques is presented.

scholarly journals 0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1383
Author(s):  
Francesco Centurelli ◽  
Giuseppe Scotti ◽  
Gaetano Palumbo
Keyword(s):  
Power Consumption ◽  
Low Voltage ◽  
Building Blocks ◽  
Frequency Divider ◽  
Cmos Process ◽  
Design Strategies ◽  
Frequency Dividers ◽  
Level Shifter ◽  
Forward Body Bias ◽  
Body Bias

Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.

scholarly journals An Ultra-Low-Power Bit-Serial Variable-Accuracy FFT Processor

2018 ◽  
Author(s):  
Yue Lu ◽  
Tom Kazmierski
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Energy Use ◽  
Low Voltage ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Simple Modification ◽  
Fft Processor ◽  
Gate Count ◽  
Bit Serial

In this paper, a new approach is proposed for designing ultra-low-power FFT (Fast Fourier Transform) system suitable for use in energy harvesting powered sensors. Bit-serial architecture is adopted to reduce the power consumption of butterfly operation. Simulation results show that, compared with state-of-the-art bit-serial and conventional parallel processors, the proposed technique is superior in terms of silicon area, power consumption, dynamic energy use due to variable precision arithmetic. A sample design of a 64-point FFT shows that the implementation can save about 40% area and 36% leakage power compared with a conventional parallel counterpart, accordingly achieving significant power benefits at a low sample rate and low voltage domain. The dynamic variation of the arithmetic precision can be achieved through a simple modification of the controller with hardware area overhead of 10% gate count.

Fabrication of spin torque devices by using quasi-antiferromagnetic materials

Impact ◽  
2020 ◽  
Vol 2020 (1) ◽  
pp. 79-81
Author(s):  
Hiromi Yuasa
Keyword(s):  
Energy Harvesting ◽  
Power Consumption ◽  
Low Power ◽  
Energy Efficient ◽  
Spin Current ◽  
Low Power Consumption ◽  
Spin Torque ◽  
Ultra Low Power ◽  
Magnetic Structures ◽  
Antiferromagnetic Materials

The devices we use on a day-to-day basis require a substantial amount of energy to power, but even more energy is left unused and goes to waste. What if our devices were (at least nearly) completely energy efficient? This would help pave the way towards a greener and more energy smart future. This concept is something one team of Japanese researchers is working on, by using quasi antiferromagnetic (AFM) materials which work successfully at the nanoscale. Professor Hiroma Yuasa is based at Kyushu University, Japan, where her laboratory is working on spintronics research. Currently, her focus includes spin current physics and spin torque in artificial magnetic structures, including the applications of these, such as in energy harvesting and ultra-low power consumption devices, which could help in achieving a greener future.

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