A PLACEMENT FLOW FOR VERY LARGE-SCALE MIXED-SIZE CIRCUIT PLACEMENT

2014 ◽  
Vol 23 (02) ◽  
pp. 1450016
Author(s):  
JIANLI CHEN ◽  
WENXING ZHU
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Main Idea ◽  
Placement Problem ◽  
Circuit Element ◽  
Solution Quality ◽  
Macro Cell ◽  
Circuit Elements ◽  
Cell Placement ◽  
Circuit Placement

The very large-scale integrated circuit (VLSI) placement problem is to determine the exact location of each movable circuit element within a given region. It is a crucial process in physical design, since it affects performance, power consumption, routability, and heat distribution of a design. In this paper, we propose a VLSI placement flow to handle the large-scale mixed-size placement problem. The main idea of our placement flow is using a floorplanning algorithm to guide the placement of circuit elements. It consists of four steps: (1) With the multilevel framework, circuit elements are clustered into blocks by recursively partitioning; (2) a floorplanning algorithm is performed on every level of the blocks; (3) the macro cells are shifted by a macro shifting technique to determine their exact locations; (4) with each macro cell location fixed, a standard cell placement algorithm is applied to place the remaining objects. The proposed approach is tested on the IBM mixed-size benchmarks and the modern mixed-size (MMS) placement benchmarks. Experimental results show that our approach outperforms the state-of-the-art placers on the solution quality for most of the benchmarks.

Effective Memetic Algorithms for VLSI Design = Genetic Algorithms + Local Search + Multi-Level Clustering

2004 ◽  
Vol 12 (3) ◽  
pp. 327-353 ◽  
Author(s):  
Shawki Areibi ◽  
Zhen Yang
Keyword(s):  
Genetic Algorithms ◽  
Local Search ◽  
Optimization Problems ◽  
Memetic Algorithms ◽  
Vlsi Circuit ◽  
Circuit Partitioning ◽  
Placement Problem ◽  
Solution Quality ◽  
Combinatorial Optimization Problems ◽  
Cell Placement

Combining global and local search is a strategy used by many successful hybrid optimization approaches. Memetic Algorithms (MAs) are Evolutionary Algorithms (EAs) that apply some sort of local search to further improve the fitness of individuals in the population. Memetic Algorithms have been shown to be very effective in solving many hard combinatorial optimization problems. This paper provides a forum for identifying and exploring the key issues that affect the design and application of Memetic Algorithms. The approach combines a hierarchical design technique, Genetic Algorithms, constructive techniques and advanced local search to solve VLSI circuit layout in the form of circuit partitioning and placement. Results obtained indicate that Memetic Algorithms based on local search, clustering and good initial solutions improve solution quality on average by 35% for the VLSI circuit partitioning problem and 54% for the VLSI standard cell placement problem.

scholarly journals Macro-Cell Placement for Custom-Chip Design Using Self-Organizing Fuzzy Technique

VLSI Design ◽  
1998 ◽  
Vol 7 (4) ◽  
pp. 385-399
Author(s):  
Ray-I Chang ◽  
Pei-Yung Hsiao
Keyword(s):  
Expert Knowledge ◽  
Optimization Technique ◽  
Parallel Architecture ◽  
Hopfield Network ◽  
Placement Problem ◽  
Chip Design ◽  
Macro Cell ◽  
Large Size ◽  
Cell Placement ◽  
Self Organizing

In this paper, a new optimization technique called SOFT(self-organizing fuzzy technique) is proposed to solve the macro-cell placement problem. In SOFT, different criteria are simultaneously accounted by a novel fuzzy gain function which models expert knowledge to control the optimization process. The presented procedure is an adaptation of Kohonen's self-organization algorithm which is well suited for implementation on massively parallel architecture for fast computing. The MCNC benchmark examples are presented to verify the performance and feasibility of SOFT. Comparisons are made with the Hopfield network, SOAP and TimberWolf MC5.6. Experiments show that the proposed method yields an average of 17% improvement in total wire length compared with previous methods. Large size problems with 225 and 1024 arbitrarily-sized macrocells are also presented.

Digital Logic Synthesis for 470 Celsius Silicon Carbide Electronics

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000064-000070
Author(s):  
N. Chiolino ◽  
A. M. Francis ◽  
J. Holmes ◽  
M. Barlow
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuit ◽  
Computer Aided Design ◽  
Large Scale ◽  
Logic Synthesis ◽  
Digital Design ◽  
Design Flow ◽  
Cmos Process ◽  
Cell Placement

Abstract Advancements in Silicon Carbide (SiC) digital integrated circuit (IC) design have enabled the ability to design complex, dense, digital blocks. Because of the large number of transistors, these complex digital designs make the time and risk of hand-crafted digital design, which has been the norm for SiC, too costly and risky. For large scale integrated digital circuits, computer aided design (CAD) tools are necessary, specifically the use of automatic synthesis, rule-based placement and signal routing software. The tools are used in progression as a design flow and are necessary for the timely and accurate creation of high-density digital designs. Application of an automated digital design flow to high-temperature SiC processes presents new challenges, such as extraction of timing characteristics at high temperatures, specifically above 400°C, as well as managing the complexity of synthesis, optimization of cell placement, verification of timing enclosure, and identifying routing constraints. These activities all require a willingness to extend and enhance the CAD software. Presented is a high temperature SiC digital synthesis flow. This flow is fully integrated with the characterization of a standard cell library that considers the variation of voltage, temperature, and process characteristics. A digital controller for a 10,000-pixel UV focal plan array (FPA) in a SiC CMOS process was designed using this high temperature digital flow. The controller is comprised of a finite state machine (FSM), that monitors several counters, shift registers and combinational logic feedback signals. The FSM is configured to optimize the FPA for different applications and exposures. The Register-Transfer Level (RTL) design of the FSM produces between 900 and 1,000 gates, depending on the temperature-dependent time closure with a total footprint of 14mm2. Typical SiC processes present a non-monotonic clock speed over temperature. The advantage of this digital design flow is that it allows the designer to target a temperature corner for the netlist design but verify its operation over a > 400°C operating range. This flow is currently being enhanced for use with NASA's SiC JFET-R process to create a high temperature communication protocol interface.

scholarly journals Enhancing Q-Factor in a Biquadratic Bandpass Filter Implemented with Opamps

Technologies ◽  
2019 ◽  
Vol 7 (3) ◽  
pp. 64 ◽  
Author(s):  
Esteban Tlelo-Coyotecatl ◽  
Alejandro Díaz-Sánchez ◽  
José Miguel Rocha-Pérez ◽  
Jose Luis Vázquez-González ◽  
Luis Abraham Sánchez-Gaspariano ◽  
...  
Keyword(s):  
Sensitivity Analysis ◽  
Integrated Circuit ◽  
Bandpass Filter ◽  
Filter Design ◽  
Q Factor ◽  
Central Frequency ◽  
Circuit Element ◽  
Biquadratic Filter ◽  
Circuit Elements ◽  
Circuit Technology

Active filter design is a mature topic that provides good solutions that can be implemented using discrete devices or integrated circuit technology. For instance, when the filter topologies are implemented using commercially available operational amplifiers (opamps), one can explore varying circuit parameters to tune the central frequency or enhance the quality (Q) factor. We show the addition of a feedback loop in the signal flow graph of a biquadratic filter topology, which enhances Q and highlights that a sensitivity analysis can be performed to identify which circuit elements influence central frequency, Q, or both. In this manner, we show the opamp-based implementation of a biquadratic bandpass filter, in which Q is enhanced through performing a sensitivity analysis for each circuit element. Equations for the central frequency and Q are provided to observe that there is not a direct parameter that enhances them, but we show that from sensitivity analysis one can identify the circuit elements that better enhance Q-factor.

scholarly journals Solving Cell Placement Problem Using Harmony Search Algorithms

2018 ◽  
Vol 8 (4) ◽  
pp. 3172-3176
Author(s):  
R. M. Al Qasem ◽  
S. M. Massadeh
Keyword(s):  
Heuristic Algorithms ◽  
Search Algorithm ◽  
Harmony Search ◽  
Optimal Solution ◽  
Harmony Search Algorithm ◽  
Placement Problem ◽  
Solution Quality ◽  
Chip Design ◽  
Cell Placement ◽  
Placement Algorithm

Cell placement is a phase in the chip design process, in which cells are assigned to physical locations. A placement algorithm is a way that satisfies the objectives and minimizes the total area while keeping enough space for routing. Cell placement is an NP-complete problem of very large size. In order to solve this problem, diversified heuristic algorithms are used. In this work, a new algorithm is proposed based on the harmony search algorithm. The harmony search algorithm mimics music improvisation process to find the optimal solution. Cell placement problem has many constraints, so in this work, the harmony search algorithm is modified to adapt to these constraints. Experiment results show that this algorithm is efficient for solving cell placement and is characterized by good performance, solution quality and likelihood of optimality.

scholarly journals A Simulated Annealing Based Centre of Mass (SAC) Approach for Mesh Routers Placement in Rural Areas

2020 ◽  
Vol 11 (1) ◽  
pp. 37-65
Author(s):  
Jean Louis Kedieng Ebongue Fendji ◽  
Chris Thron
Keyword(s):  
Simulated Annealing ◽  
Rural Areas ◽  
Large Scale ◽  
Mesh Network ◽  
Convergence Time ◽  
Centre Of Mass ◽  
Placement Problem ◽  
Solution Quality ◽  
Wireless Mesh ◽  
Area Of Interest

The problem of node placement in a rural wireless mesh network (RWMN) consists of determining router placement which minimizes the number of routers while providing good coverage of the area of interest. This problem is NP-hard with a factorial complexity. This article introduces a new approach, called the simulated annealing-based centre of mass (SAC) for solving this placement problem. The intent of this approach is to improve the robustness and the quality of solution, and to minimize the convergence time of a simulated annealing (SA) approach in solving the same problem in small and large scale. SAC is compared to the centre of mass (CM) and simulated annealing (SA) approaches. The performances of these algorithms were evaluated on a set of 24 instances. The experimental results show that the SAC approach provides the best robustness and solution quality, while decreasing by half the convergence time of the SA algorithm.

scholarly journals Fast Heuristic Optimization Methods for Point Label Placement Problem

2018 ◽  
pp. 162-167
Author(s):  
Orkun Akile ◽  
Erdogan Sevilgen
Keyword(s):  
Large Scale ◽  
Optimization Methods ◽  
Heuristic Optimization ◽  
Graphical Display ◽  
Placement Problem ◽  
Solution Quality ◽  
Label Placement ◽  
Local Search Methods ◽  
Display Systems ◽  
Potential Use

Point label placement problem is the problem of labeling points in graphical display systems such as mapbased ones in order to minimize conflicts of labels and thus to maximize legibility. Algorithmic complexity of the general problem is proven to be NP-hard. Addressing this problem is becoming more important in dynamic and real-time environments, where both display properties or point elements are subject to change, since those systems have potential use widely and in large scale. In this study, heuristic optimization methods are proposed to facilitate fast and goodquality labeling in such dynamic environments. The methods are two-phased and comprised of several combinations of greedy construction and local search methods. Performances of the methods are examined in terms of solution quality and run time. The eliminative, two-criteria method outperform other methods in this study and the methods proposed in the literature.

Evolution of Hardware Morphology of Large-Scale Computers and the Trend of Space Allocation for Thermal Management

2016 ◽  
Vol 139 (1) ◽  
Author(s):  
Wataru Nakayama
Keyword(s):  
Thermal Management ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Geometric Model ◽  
System Size ◽  
Primary Concern ◽  
Multichip Modules ◽  
Circuit Element ◽  
Technology Node

Thermal management of very large-scale computers will have to leave the traditional well-beaten path. Up to the present time, the primary concern has been with rising heat flux on the integrated circuit chip, while a space has been available for the implementation of high-performance cooling design. In future systems, the spatial constraint will become a primary determinant of thermal management methodology. To corroborate this perspective, the evolution of computer's hardware morphology is simulated. Simulation tool is the geometric model, where the model structure is composed of circuit cells and platforms for circuit blocks. The cell is the minimum circuit element whose size is pegged to the technology node, while the total number of cells represents the system size. The platforms are the models of microprocessor chips, multichip modules (MCMs), and printed wiring boards (PWBs). The major points of discussion are as follows: (1) The system morphology is dictated by the competition between the progress of technology node and the demand for increase in the system size. (2) Only where the miniaturization of cells is achieved so as to deploy a system on a few PWBs, ample space is created for thermal management. (3) In the future, the cell miniaturization will hit the physical limit, while the demand for larger systems will be unabated. Liquid cooling, where the coolant is driven through very long microchannels, may provide a viable thermal solution.

scholarly journals A Review on Terahertz Technologies Accelerated by Silicon Photonics

Nanomaterials ◽  
2021 ◽  
Vol 11 (7) ◽  
pp. 1646
Author(s):  
Jingya Xie ◽  
Wangcheng Ye ◽  
Linjie Zhou ◽  
Xuguang Guo ◽  
Xiaofei Zang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Silicon Photonics ◽  
Large Scale ◽  
Cost Effective ◽  
Single Chip ◽  
Photonic Integrated Circuit ◽  
Hybrid Silicon ◽  
The Cost ◽  
Silicon Based ◽  
Thz Applications

In the last couple of decades, terahertz (THz) technologies, which lie in the frequency gap between the infrared and microwaves, have been greatly enhanced and investigated due to possible opportunities in a plethora of THz applications, such as imaging, security, and wireless communications. Photonics has led the way to the generation, modulation, and detection of THz waves such as the photomixing technique. In tandem with these investigations, researchers have been exploring ways to use silicon photonics technologies for THz applications to leverage the cost-effective large-scale fabrication and integration opportunities that it would enable. Although silicon photonics has enabled the implementation of a large number of optical components for practical use, for THz integrated systems, we still face several challenges associated with high-quality hybrid silicon lasers, conversion efficiency, device integration, and fabrication. This paper provides an overview of recent progress in THz technologies based on silicon photonics or hybrid silicon photonics, including THz generation, detection, phase modulation, intensity modulation, and passive components. As silicon-based electronic and photonic circuits are further approaching THz frequencies, one single chip with electronics, photonics, and THz functions seems inevitable, resulting in the ultimate dream of a THz electronic–photonic integrated circuit.

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