Digital Logic Synthesis for 470 Celsius Silicon Carbide Electronics

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000064-000070
Author(s):  
N. Chiolino ◽  
A. M. Francis ◽  
J. Holmes ◽  
M. Barlow
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuit ◽  
Computer Aided Design ◽  
Large Scale ◽  
Logic Synthesis ◽  
Digital Design ◽  
Design Flow ◽  
Cmos Process ◽  
Cell Placement

Abstract Advancements in Silicon Carbide (SiC) digital integrated circuit (IC) design have enabled the ability to design complex, dense, digital blocks. Because of the large number of transistors, these complex digital designs make the time and risk of hand-crafted digital design, which has been the norm for SiC, too costly and risky. For large scale integrated digital circuits, computer aided design (CAD) tools are necessary, specifically the use of automatic synthesis, rule-based placement and signal routing software. The tools are used in progression as a design flow and are necessary for the timely and accurate creation of high-density digital designs. Application of an automated digital design flow to high-temperature SiC processes presents new challenges, such as extraction of timing characteristics at high temperatures, specifically above 400°C, as well as managing the complexity of synthesis, optimization of cell placement, verification of timing enclosure, and identifying routing constraints. These activities all require a willingness to extend and enhance the CAD software. Presented is a high temperature SiC digital synthesis flow. This flow is fully integrated with the characterization of a standard cell library that considers the variation of voltage, temperature, and process characteristics. A digital controller for a 10,000-pixel UV focal plan array (FPA) in a SiC CMOS process was designed using this high temperature digital flow. The controller is comprised of a finite state machine (FSM), that monitors several counters, shift registers and combinational logic feedback signals. The FSM is configured to optimize the FPA for different applications and exposures. The Register-Transfer Level (RTL) design of the FSM produces between 900 and 1,000 gates, depending on the temperature-dependent time closure with a total footprint of 14mm2. Typical SiC processes present a non-monotonic clock speed over temperature. The advantage of this digital design flow is that it allows the designer to target a temperature corner for the netlist design but verify its operation over a > 400°C operating range. This flow is currently being enhanced for use with NASA's SiC JFET-R process to create a high temperature communication protocol interface.

Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Synthesis ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Timing Models ◽  
High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

Digital and Analogue Integrated Circuits in Silicon Carbide for High Temperature Operation

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000373-000377 ◽  
Author(s):  
E.P Ramsay ◽  
D.T. Clark ◽  
J.D. Cormack ◽  
A.E. Murphy ◽  
D.A Smith ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Nand Gate ◽  
Cmos Process ◽  
Flip Flop ◽  
Aero Engines ◽  
Simple Logic ◽  
High Temperature Operation

A need for high temperature integrated circuits is emerging in a number of application areas. As Silicon Carbide power discrete devices become more widely available, there is a growing need for control ICs capable of operating at the same temperatures and mounted on the same modules. Also, the use of high temperature sensors, in, for example, aero engines and in deep hydrocarbon and geothermal drilling applications results in a demand for high temperature sensor interface ICs. This paper presents new results on a range of simple logic and analogue circuits fabricated on a developing Silicon Carbide CMOS process which is intended for mixed signal integrated circuit applications such as those above. A small family of logic circuits, pin compatible with the 74xx series TTL logic parts, has been designed, fabricated and tested and includes, for example, a Quad Nand gate and a Dual D-type flip-flop. These have been found to be functional from room temperature up to 400°C. Analogue blocks have been investigated with a view to using switched capacitor or autozero techniques to compensate for temperature and time induced drifts, allowing very high temperature operation.

High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000242-000248 ◽  
Author(s):  
A. Matthew Francis ◽  
Jim Holmes ◽  
Nick Chiolino ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Synthesis ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Mos Devices ◽  
Timing Models

Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

CMOS Circuits on Silicon Carbide for High Temperature Operation

2014 ◽  
Vol 1693 ◽  
Author(s):  
David T. Clark ◽  
Robin F. Thompson ◽  
Aled E. Murphy ◽  
David A. Smith ◽  
Ewan P. Ramsay ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Wide Temperature Range ◽  
Integrated Circuit ◽  
Elevated Temperatures ◽  
Logic Circuits ◽  
Digital Logic ◽  
Cmos Integrated Circuit ◽  
Temperature Range ◽  
Simple Logic

ABSTRACTWe present the characteristics of a high temperature CMOS integrated circuit process based on 4H silicon carbide designed to operate at temperatures beyond 300°C. N-channel and P-channel transistor characteristics at room and elevated temperatures are presented. Both channel types show the expected low values of field effect mobility well known in SiC MOSFETS. However the performance achieved is easily capable of exploitation in CMOS digital logic circuits and certain analogue circuits, over a wide temperature range.Data is also presented for the performance of digital logic demonstrator circuits, in particular a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. Devices are packaged in high temperature ceramic dual in line (DIL) packages, which are capable of greater than 300°C operation. A high temperature “micro-oven” system has been designed and built to enable testing and stressing of units assembled in these package types. This system heats a group of devices together to temperatures of up to 300°C while keeping the electrical connections at much lower temperatures. In addition, long term reliability data for some structures such as contact chains to n-type and p-type SiC and simple logic circuits is summarized.

500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000076-000083 ◽  
Author(s):  
Paul Shepherd ◽  
Ashfaqur Rahman ◽  
Shamim Ahmed ◽  
A Matt Francis ◽  
Jim Holmes ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Extreme Environments ◽  
Phase Locked Loops ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Fully Integrated ◽  
Improved Performance

Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.

Operation of Silicon Carbide Integrated Circuits under High Temperature and Pressure

2017 ◽  
Vol 2017 (1) ◽  
pp. 000526-000530
Author(s):  
M. Barlow ◽  
A. M. Francis ◽  
J. Holmes
Keyword(s):  
Silicon Carbide ◽  
High Pressure ◽  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Leading Edge ◽  
Limited Information ◽  
High Temperature And Pressure ◽  
Temperature And Pressure

Abstract Silicon carbide integrated circuits have demonstrated the ability to function at temperatures as high as 600 °C for extended periods of time. Many environments where high temperature in-situ electronics are desired also have large pressures as well. While some validation has been done for high pressure environments, limited information on the parametric impact of pressure on SiC integrated circuits is available. This paper takes two leading-edge SiC integrated circuit processes using two different classes of devices (JFET and CMOS), and measures the performance through temperature and pressure variation. Circuit functionality was verified at high temperature (475 °C) as well as high pressure (1700 psig).

Optimisation of 4H-SiC Enhancement Mode JFETs for High Performance and Energy Efficient Digital Logic in Extreme Environments

2011 ◽  
Vol 413 ◽  
pp. 391-398 ◽  
Author(s):  
Hassan Habib ◽  
Nicholas Wright ◽  
Alton B. Horsfall
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Energy Efficient ◽  
Computer Aided Design ◽  
High Performance ◽  
Extreme Environments ◽  
Enhancement Mode ◽  
Power Resources ◽  
Commercial Device ◽  
Aided Design

The commercialisation of Silicon Carbide devices and circuits require high performance, miniaturised devices which are energy efficient and can function on the limited power resources available in harsh environments. The high temperature Technology Computer Aided Design (TCAD) simulation model has been used to design and optimise a potential commercial device to meet the current challenges faced by Silicon Carbide technology. In this paper we report a new methodology to optimise the design of high temperature four terminal enhancement mode n-and p-JFETs for Complementary JFET (CJFET) logic.

High Temperature CMOS Circuits on Silicon Carbide

2015 ◽  
Vol 821-823 ◽  
pp. 859-862 ◽  
Author(s):  
E. Ramsay ◽  
James Breeze ◽  
David T. Clark ◽  
A. Murphy ◽  
D. Smith ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
Cmos Process ◽  
Low Leakage ◽  
Current Path ◽  
Pulse Width Modulator ◽  
Wide Range ◽  
And Performance

This paper presents the characteristics and performance of a range of Silicon Carbide (SiC) CMOS integrated circuits fabricated using a process designed to operate at temperatures of 300°C and above. The properties of Silicon carbide enable both n-channel and p-channel MOSFETS to operate at temperatures above 400°C [1] and we are developing a CMOS process to exploit this capability [4]. The operation of these transistors and other integrated circuit elements such as resistors and contacts is presented across a temperature range of room temperature to +400°C. We have designed and fabricated a wide range of test and demonstrator circuits. A set of six simple logic parts, such as a quad NAND and NOR gates, have been stressed at 300°C for extended times and performance results such as propagation delay drive levels, threshold levels and current consumption versus stress time are presented. Other circuit implementations, with increased logic complexity, such as a pulse width modulator, a configurable timer and others have also been designed, fabricated and tested. The low leakage characteristics of SiC has allowed the implementation of a very low leakage analogue multiplexer showing less than 0.5uA channel leakage at 400°C. Another circuit implemented in SiC CMOS demonstrates the ability to drive SiC power switching devices. The ability of CMOS to provide an active pull up and active pull down current can provide the charging and discharging current required to drive a power MOSFET switch in less than 100ns. Being implemented in CMOS, the gate drive buffer benefits from having no direct current path from the power rails, except during switching events. This lowers the driver power dissipation. By including multiple current paths through independently switched transistors, the gate drive buffer circuit can provide a high switching current and then a lower sustaining current as required to minimize power dissipation when driving a bipolar switch.

A PLACEMENT FLOW FOR VERY LARGE-SCALE MIXED-SIZE CIRCUIT PLACEMENT

2014 ◽  
Vol 23 (02) ◽  
pp. 1450016
Author(s):  
JIANLI CHEN ◽  
WENXING ZHU
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Main Idea ◽  
Placement Problem ◽  
Circuit Element ◽  
Solution Quality ◽  
Macro Cell ◽  
Circuit Elements ◽  
Cell Placement ◽  
Circuit Placement

The very large-scale integrated circuit (VLSI) placement problem is to determine the exact location of each movable circuit element within a given region. It is a crucial process in physical design, since it affects performance, power consumption, routability, and heat distribution of a design. In this paper, we propose a VLSI placement flow to handle the large-scale mixed-size placement problem. The main idea of our placement flow is using a floorplanning algorithm to guide the placement of circuit elements. It consists of four steps: (1) With the multilevel framework, circuit elements are clustered into blocks by recursively partitioning; (2) a floorplanning algorithm is performed on every level of the blocks; (3) the macro cells are shifted by a macro shifting technique to determine their exact locations; (4) with each macro cell location fixed, a standard cell placement algorithm is applied to place the remaining objects. The proposed approach is tested on the IBM mixed-size benchmarks and the modern mixed-size (MMS) placement benchmarks. Experimental results show that our approach outperforms the state-of-the-art placers on the solution quality for most of the benchmarks.

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