A VERY LOW-TC SECOND-ORDER TEMPERATURE-COMPENSATED CMOS CURRENT REFERENCE

2014 ◽  
Vol 23 (03) ◽  
pp. 1450042 ◽  
Author(s):  
LIANG LIANG ◽  
ZHANGMING ZHU ◽  
YINTANG YANG
Keyword(s):  
Temperature Compensation ◽  
Supply Voltage ◽  
Design Method ◽  
Current Source ◽  
Second Order ◽  
Cmos Process ◽  
Current Mirror ◽  
First Order ◽  
Temperature Range ◽  
Current Reference

This paper proposes a novel second-order temperature-compensated CMOS current reference which exploits a new self-biased current source for first-order temperature compensation and a resistor-free widlar current mirror for second-order temperature compensation. Moreover, by deriving the temperature coefficient (TC) of the reference current, the temperature compensation condition equations together with a design method of minimizing the thermal drift in a required temperature range are presented. Based on these, the circuit is designed in a standard 0.18 μm CMOS process and achieves a very low TC of only 16.9 ppm/°C in a temperature range between -40°C and 120°C, with 1 μA reference current at 27°C. Besides, the current reference can operate at supply voltage down to 1.3 V, with a good supply regulation of 0.5%/V. At 27°C, its power consumption is 8.93 μW.

Tunable CMOS Active Inductor Using Widlar Current Source

2018 ◽  
Vol 28 (02) ◽  
pp. 1950027 ◽  
Author(s):  
Dhara P Patel ◽  
Shruti Oza-Rahurkar
Keyword(s):  
Quality Factor ◽  
Supply Voltage ◽  
Noise Analysis ◽  
Current Source ◽  
Cmos Technology ◽  
The Other ◽  
Active Inductor ◽  
Voltage Sensitivity ◽  
Current Mirror ◽  
Characterization Factors

A novel tuning principle for simple gyrator-based CMOS active inductor (AI) circuit is presented. The method makes use of Widlar current source to enhance the quality factor. The simulation of the proposed AI provides a maximum quality factor of 1819 at 2.88[Formula: see text]GHz. The AI shows the inductive bandwidth of 1.66[Formula: see text]GHz to 3.16[Formula: see text]GHz and power consumption of 6.87[Formula: see text]mW. The other characterization factors such as linearity, supply voltage sensitivity and noise analysis are discussed. The performance of the tunable AI using Widlar current source are compared with the same using a simple current mirror. An AI using a conventional current mirror (CCM) and Widlar current source have been implemented in the 0.18[Formula: see text][Formula: see text]m CMOS technology.

PRECISING COMPLEX-COMPENSATED CURRENT REFERENCE BASED ON DIFFERENTIAL MODE OF CURRENTS

2012 ◽  
Vol 21 (07) ◽  
pp. 1250059 ◽  
Author(s):  
L. F. SHI ◽  
Y. ZHAO ◽  
W. G. JIA ◽  
L. Y. CHENG ◽  
X. Q. LAI
Keyword(s):  
Temperature Coefficient ◽  
Temperature Compensation ◽  
Negative Temperature Coefficient ◽  
Supply Voltage ◽  
Negative Temperature ◽  
Differential Mode ◽  
Temperature Coefficients ◽  
Current Reference ◽  
Nonlinear Temperature ◽  
A Current

A current reference with complex compensation using negative temperature coefficient of multiple currents is proposed. The principle of compensation is introduced in detail. This work generates two different compensated currents in the whole temperature range, which is different from the traditional curvature-compensated circuit. The compensation is achieved by using difference of the negative temperature coefficients. Piecewise curvature-compensation and higher order nonlinear temperature compensation are applied at the same time. The proposed circuit is simple and easy to implement. Results of simulation with HSPICE show that the achieved temperature coefficient is only 34.2 ppm/°C compared with 364 ppm/°C under 1 μm BCD process, which is unnecessary to compensate in the range of -25°C ∼ 125°C at 5 V supply voltage.

A low power trimming-free CMOS relaxation oscillator with process and temperature compensation

2020 ◽  
Vol 34 (16) ◽  
pp. 2050176
Author(s):  
Yao Wang ◽  
Mengmeng Yao ◽  
Zhaolei Wu ◽  
Lijun Sun ◽  
Juin Jei Liou
Keyword(s):  
Temperature Compensation ◽  
Supply Voltage ◽  
Relaxation Oscillator ◽  
Oscillation Period ◽  
Frequency Variation ◽  
Cmos Process ◽  
Temperature Variations ◽  
Simulated Temperature ◽  
On Chip ◽  
Rc Time Constant

The design of a 22 KHz 358 nW CMOS relaxation oscillator with a process and temperature compensation scheme is presented. Instead of the commonly used RC time constant, the oscillation period of the proposed circuit is determined by the resistance ratio of several resistors, which is insensitive to process and temperature variations. The on-chip relaxation oscillator is simulated in a 0.18 [Formula: see text]m CMOS process. Without any calibration or off-chip components, the frequency variation of the proposed oscillator is ±[Formula: see text]3.24% across [Formula: see text] to 100[Formula: see text]C temperature range and 5 different process corners. Compared to the conventional relaxation oscillator, the frequency variation of this circuit is reduced by 89%. The simulated temperature coefficient is 111 ppm/[Formula: see text]C, and the frequency variation over the supply voltage from 1.2 V to 1.7 V is 2.1%/V. The typical power consumption of the proposed circuit is 358 nW.

DESIGN OF A CMOS BANDGAP REFERENCE CIRCUIT WITH A WIDE TEMPERATURE RANGE, HIGH PRECISION AND LOW TEMPERATURE COEFFICIENT

2014 ◽  
Vol 23 (08) ◽  
pp. 1450107 ◽  
Author(s):  
JUN-DA CHEN ◽  
CHENG-KAI YE
Keyword(s):  
Temperature Coefficient ◽  
High Precision ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Reference ◽  
Temperature Range ◽  
Wide Range ◽  
Bandgap Voltage Reference ◽  
Reference Circuit ◽  
Cmos Voltage Reference

This paper presents an approach to the design of a high-precision CMOS voltage reference. The proposed circuit is designed for TSMC 0.35 μm standard CMOS process. We design the first-order temperature compensation bandgap voltage reference circuit. The proposed post-simulated circuit delivers an output voltage of 0.596 V and achieves the reported temperature coefficient (TC) of 3.96 ppm/°C within the temperature range from -60°C to 130°C when the supply voltage is 1.8 V. When simulated in a smaller temperature range from -40°C to 80°C, the circuit achieves the lowest reported TC of 2.09 ppm/°C. The reference current is 16.586 μA. This circuit provides good performances in a wide range of temperature with very small TC.

scholarly journals Nano Power Current Reference Circuit Consisting of Sub-threshold CMOS Circuits

2019 ◽  
Vol 9 (1) ◽  
pp. 4657-4660
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Current Source ◽  
Threshold Power ◽  
Threshold Region ◽  
Voltage Range ◽  
Simulation Performance ◽  
Current Reference ◽  
Reference Circuit

a low voltage CMOS Nano power current reference circuit has been presented in this paper and also the circuit simulation performance in 180-nm UMC CMOS technology. Most of the MOSFETs operate in sub-threshold region consisting of bias-voltage, start-up and current-source sub-circuits. A stable reference current of 4-nA lying in supply voltage range of 1 V-1.8 V has been generated with line sensitivity of 0.203% /V. Within the temperature range of 0°C to 100 °C, and the voltage level of 1.8 V, the temperature coefficient was 7592ppm/°C. At the same voltage supply, the power dissipation was found out to be 380 NW. It is suitable to use this circuit in sub threshold power aware large scale integration.

EXCHANGE REACTIONS OF IODIDE ION WITH AROMATIC IODIDES

1951 ◽  
Vol 29 (2) ◽  
pp. 154-161 ◽  
Author(s):  
A. M. Kristjanson ◽  
C. A. Winkler
Keyword(s):  
Activation Energies ◽  
Second Order ◽  
Exchange Reactions ◽  
First Order ◽  
Temperature Range ◽  
Iodide Ion

The exchange reactions of iodide ion with o- and p-nitroiodobenzene in the temperature range about 170°–238°C were apparently second order with activation energies of approximately 29 and 33.5 kcal. per mole respectively. In the same temperature range the exchange of iodide ion with iodobenzene and m-nitroiodobenzene appeared to be first order reactions, with activation energies of approximately 25 kcal. per mole.

Nano Power Current Reference Circuit consisting of Sub-threshold CMOS Circuits

2017 ◽  
Vol 2 (1) ◽  
pp. 1-4
Author(s):  
Dinesh Kushwaha ◽  
D. K. Mishra
Keyword(s):  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Current Source ◽  
Cmos Technology ◽  
Threshold Region ◽  
Voltage Range ◽  
Current Reference ◽  
Reference Circuit

This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180- nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, current-source sub-circuits with most of the MOSFETs operating in sub-threshold region. Simulation results shows that the circuit generates a stable reference current of 4-nA in supply voltage range 1 V- 1.8 V with line sensitivity of 0.203%/V.The temperature coefficient of the current was 7592ppm/°C at 1.8 V in the range of 0°C-100°C. The power dissipation was 380 NW at 1.8 V Supply. The proposed circuit would be suitable for use in sub-threshold –operated power-aware large-scale integration

The Design of Bandgap Reference Based on Empyrean Aether Software

2014 ◽  
Vol 687-691 ◽  
pp. 3489-3493
Author(s):  
Wei Qu ◽  
Li Mei Hou ◽  
Xiao Xin Sun ◽  
Jing Yu Sun ◽  
Liang Yu Li
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
Design Method ◽  
Reference Voltage ◽  
Voltage Source ◽  
Reference Source ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Voltage ◽  
Reference Voltage Source

A high-performance bandgap reference voltage source design method is proposed in this paper, according to the shortcomings of traditional bandgap reference voltage source. This method combined CSMC 0.35μm CMOS process with Aether software technology, enabling to improve the bandgap reference source op amp performance and take into account accuracy and stability of the system. From the experimental results: this bandgap reference voltage source output voltage has changed about 63 mV when the temperature varied from to , and the line regulator is 0.4mV/V when the power supply voltage varied from 3.2V to 3.3V. This system has advantages of high accuracy and good stability.

12-BIT PSEUDO-DIFFERENTIAL CURRENT-SOURCE RESISTOR-STRING HYBRID DAC

2011 ◽  
Vol 20 (04) ◽  
pp. 709-725 ◽  
Author(s):  
M. T. S. AB-AZIZ ◽  
A. MARZUKI ◽  
Z. A. A. AZIZ
Keyword(s):  
Supply Voltage ◽  
Current Source ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Process Technology ◽  
Analog Converter ◽  
Final Design ◽  
Resistor String ◽  
Simulation Results ◽  
Binary Weighted

This paper discusses a hybrid Digital-Analog Converter (DAC) architecture which is a combination of a binary-weighted resistor approach for eight bits in the least-significant-bit and thermometer coded approach for four bits in the most-significant-bit. The proposed design combines advantages of the binary-weighted resistor approach and thermometer coded approach. The final design is composed of two 12-bit DACs to achieve a pseudo differential output signal. The converter was designed with a Silterra 0.18 μm 1.8 V/3.3 V CMOS process technology. The post-layout simulation results show that this design achieves 12-bit resolution with INL and DNL of 0.375 LSB and 0.25 LSB, respectively. The power consumption is 6.291 mW when the designed DAC is biased with supply voltage equal to 3 V. The performance is accomplished with a design area of 230 μm × 255 μm.

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