Compact Active Quenching Circuit for Single Photon Avalanche Diodes Arrays

2017 ◽  
Vol 26 (10) ◽  
pp. 1750149
Author(s):  
Lixia Zheng ◽  
Huan Hu ◽  
Ziqing Weng ◽  
Qun Yao ◽  
Jin Wu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Small Area ◽  
Single Photon ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Experimental Measurements ◽  
Avalanche Diode ◽  
Avalanche Diodes ◽  
Area Occupation ◽  
Sensing Time

A compact quenching circuit for Single Photon Avalanche Diode (SPAD) arrays is presented. The proposed circuit preserves the advantages of small area occupation and low power consumption, since it mainly adopts the junction capacitance of the detector to sense the avalanche current. The sensing time is now limited more by the detector rather than the circuit itself. Fabricated in TSMC standard 0.35[Formula: see text][Formula: see text]m CMOS process, the proposed circuit only occupies an area of 20[Formula: see text][Formula: see text]m[Formula: see text][Formula: see text][Formula: see text]31[Formula: see text][Formula: see text]m and can operate properly with the detector biased up to 5[Formula: see text]V above breakdown. The circuit functionality has been verified by experimental measurements, operating with 64[Formula: see text][Formula: see text][Formula: see text]64 InGaAs/InP single photon avalanche diode arrays for time-of-flight-based applications.

scholarly journals An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

Electronics ◽  
2022 ◽  
Vol 11 (2) ◽  
pp. 261
Author(s):  
Jongsun Kim
Keyword(s):  
Power Consumption ◽  
Small Area ◽  
High Speed ◽  
Propagation Delay ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Clock Generator ◽  
Frequency Multiplication ◽  
Digital Clock ◽  
Delay Locked Loop

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

scholarly journals Temporal Encoding to Reject Background Signals in a Low Complexity, Photon Counting Communication Link

Materials ◽  
2018 ◽  
Vol 11 (9) ◽  
pp. 1671 ◽  
Author(s):  
Alexander Griffiths ◽  
Johannes Herrnsdorf ◽  
Christopher Lowe ◽  
Malcolm Macdonald ◽  
Robert Henderson ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Single Photon ◽  
Photon Counting ◽  
Low Complexity ◽  
Low Power Consumption ◽  
Communication Link ◽  
Free Space Optical ◽  
Received Power ◽  
Temporal Encoding

Communicating information at the few photon level typically requires some complexity in the transmitter or receiver in order to operate in the presence of noise. This in turn incurs expense in the necessary spatial volume and power consumption of the system. In this work, we present a self-synchronised free-space optical communications system based on simple, compact and low power consumption semiconductor devices. A temporal encoding method, implemented using a gallium nitride micro-LED source and a silicon single photon avalanche photo-detector (SPAD), demonstrates data transmission at rates up to 100 kb/s for 8.25 pW received power, corresponding to 27 photons per bit. Furthermore, the signals can be decoded in the presence of both constant and modulated background noise at levels significantly exceeding the signal power. The system’s low power consumption and modest electronics requirements are demonstrated by employing it as a communications channel between two nano-satellite simulator systems.

scholarly journals Photon-Detection-Probability Simulation Method for CMOS Single-Photon Avalanche Diodes

Sensors ◽  
2020 ◽  
Vol 20 (2) ◽  
pp. 436 ◽  
Author(s):  
Chin-An Hsieh ◽  
Chia-Ming Tsai ◽  
Bing-Yue Tsui ◽  
Bo-Jen Hsiao ◽  
Sheng-Di Lin
Keyword(s):  
Detection Probability ◽  
Single Photon ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Single Photons ◽  
Photon Detection ◽  
Important Indicator ◽  
Avalanche Diodes ◽  
Single Photon Avalanche Diodes

Single-photon avalanche diodes (SPADs) in complementary metal-oxide-semiconductor (CMOS) technology have excellent timing resolution and are capable to detect single photons. The most important indicator for its sensitivity, photon-detection probability (PDP), defines the probability of a successful detection for a single incident photon. To optimize PDP is a cost- and time-consuming task due to the complicated and expensive CMOS process. In this work, we have developed a simulation procedure to predict the PDP without any fitting parameter. With the given process parameters, our method combines the process, the electrical, and the optical simulations in commercially available software and the calculation of breakdown trigger probability. The simulation results have been compared with the experimental data conducted in an 800-nm CMOS technology and obtained a good consistence at the wavelength longer than 600 nm. The possible reasons for the disagreement at the short wavelength have been discussed. Our work provides an effective way to optimize the PDP of a SPAD prior to its fabrication.

A 260-μW Down-Conversion Demodulator for MICS-Band Receiver

2016 ◽  
Vol 26 (02) ◽  
pp. 1750027 ◽  
Author(s):  
Chia-Hung Chang ◽  
Cihun-Siyong Alex Gong ◽  
Jian-Chiun Liou ◽  
Yu-Lin Tsou ◽  
Feng-Lin Shiu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Communication Services ◽  
Ultra Low Power ◽  
Resistive Feedback ◽  
Mics Band ◽  
Down Conversion ◽  
Implant Communication

This paper showcases a low-power demodulator for medical implant communication services (MICS) applications. Complementary shunt resistive feedback, current reuse configuration, and sub-threshold LO driving techniques are proposed to achieve ultra-low power consumption. The chip has been implemented in standard CMOS process and consumes only 260-[Formula: see text]W.

A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC

2011 ◽  
Vol 20 (01) ◽  
pp. 15-27 ◽  
Author(s):  
XIAN TANG ◽  
KONG PANG PUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
High Speed ◽  
High Accuracy ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Power Efficient ◽  
Successive Approximation Adc ◽  
Switched Current

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

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