Low-Voltage Diode-Less Rectifier Based on Fully Differential Difference Transconductance Amplifier

2017 ◽  
Vol 26 (11) ◽  
pp. 1750172 ◽  
Author(s):  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Montree Kumngern ◽  
Vilém Kledrowetz
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Wearable Electronics ◽  
Voltage Range ◽  
Voltage Supply ◽  
Mos Transistor ◽  
Fully Differential ◽  
Transconductance Amplifier ◽  
Multiple Input

This paper presents a voltage-mode low-voltage low-power diode-less rectifier with only one active element, the fully differential difference transconductance amplifier (FDDTA). The multiple-input floating-gate MOS (FG-MOS) transistor is used to build the differential pairs of the FDDTA resulting in the reduced count of transistors, circuit simplicity and the capability to work under low-voltage supply with extended input voltage range. The rectifier was designed with 0.9[Formula: see text]V voltage supply and 8[Formula: see text][Formula: see text]W power consumption, hence it is suitable for wearable electronics and biomedical applications. The simulation results obtained from the Cadence platform using 0.18[Formula: see text][Formula: see text]m TSMC CMOS technology show good performances for the designed circuit.

Sub-Volt Fully Balanced Differential Difference Amplifier

2014 ◽  
Vol 24 (01) ◽  
pp. 1550005 ◽  
Author(s):  
Fabian Khateb ◽  
Montree Kumngern ◽  
Spyridon Vlassis ◽  
Costas Psychalinos ◽  
Tomasz Kulej
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Voltage Range ◽  
State Variable ◽  
Low Voltage Operation ◽  
Differential Difference Amplifier ◽  
Simulation Results ◽  
State Variable Filter

This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-floating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5 V and consumes only 357 nW of power. The proposed circuit was simulated in a 0.18-μm TSMC CMOS technology and the simulation results prove its functionality and attractive parameters. An application example of a state variable filter is also presented to confirm the usefulness of the proposed BD-QFG FB-DDA.

130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications

2017 ◽  
Vol 26 (08) ◽  
pp. 1740003 ◽  
Author(s):  
Daniel Arbet ◽  
Viera Stopjaková ◽  
Martin Kováč ◽  
Lukáš Nagy ◽  
Matej Rakús ◽  
...  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Variable Gain Amplifier ◽  
Voltage Range ◽  
Variable Gain ◽  
Wide Scale ◽  
Simulation Results ◽  
Low Supply Voltage

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS

2012 ◽  
Vol 21 (03) ◽  
pp. 1250024 ◽  
Author(s):  
CHAIWAT SAKUL ◽  
KOBCHAI DEJHAN
Keyword(s):  
Relative Error ◽  
Low Voltage ◽  
Harmonic Distortion ◽  
Input Voltage ◽  
Experimental Result ◽  
Voltage Range ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
Power Dispersion ◽  
Four Quadrant

This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)

2013 ◽  
Vol 2 (1) ◽  
pp. 49
Author(s):  
Abderrezak Marzaki ◽  
V. Bidal ◽  
R. Laffont ◽  
W. Rahajandraibe ◽  
J-M. Portal ◽  
...  
Keyword(s):  
Low Voltage ◽  
Schmitt Trigger ◽  
Cmos Technology ◽  
Floating Gate ◽  
Dual Control ◽  
Switching Voltage ◽  
Voltage Range ◽  
Rail To Rail ◽  
Floating Gate Transistor ◽  
Simulation Results

This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages <em>V<sub>TH- </sub></em>(low switching voltage) and <em>V<sub>TH+ </sub></em>(high switching voltage).

scholarly journals Full-Bridge Active-Clamp Forward-Flyback Converter with an Integrated Transformer for High-Performance and Low Cost Low-Voltage DC Converter of Vehicle Applications

Energies ◽  
2020 ◽  
Vol 13 (4) ◽  
pp. 863 ◽  
Author(s):  
Jaeil Baek ◽  
Han-Shin Youn
Keyword(s):  
High Power ◽  
High Performance ◽  
Low Voltage ◽  
Low Cost ◽  
Primary Root ◽  
Input Voltage ◽  
Oxide Semiconductor ◽  
Duty Ratio ◽  
Voltage Range ◽  
Active Clamp

This paper presents a full-bridge active-clamp forward-flyback (FBACFF) converter with an integrated transformer sharing a single primary winding. Compared to the conventional active-clamp-forward (ACF) converter, the proposed converter has low voltage stress on the primary switches due to its full-bridge active-clamp structure, which can leverage high performance Silicon- metal–oxide–semiconductor field-effect transistor (Si-MOSFET) of low voltage rating and low channel resistance. Integrating forward and flyback operations allows the proposed converter to have much lower primary root mean square (RMS) current than the conventional phase-shifted-full-bridge (PSFB) converter, while covering wide input/output voltage range with duty ratio over 0.5. The proposed integrated transformer reduces the transformer conduction loss and simplify the secondary structure of the proposed converter. As a result, the proposed converter has several advantages: (1) high heavy load efficiency, (2) wide input voltage range operation, (3) high power density with the integrated transformer, and (4) low cost. The proposed converter is a very promising candidate for applications with wide input voltage range and high power, such as the low-voltage DC (LDC) converter for eco-friendly vehicles.

A Self-Starting 70 mV-1 V, 65% Peak Efficient, TEG Energy Harvesting Chip with 5 ms Startup Time

2016 ◽  
Vol 26 (03) ◽  
pp. 1750040
Author(s):  
Arun Kumar Sinha
Keyword(s):  
Peak Power ◽  
Low Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Voltage Source ◽  
Thermo Electric ◽  
Electric Generator ◽  
Measurement Results ◽  
Startup Time ◽  
Work Up

This paper presents design and measurement results of a DC–DC converter, intended to harvest energy from a thermo-electric generator (TEG). The prototype chip was fabricated in 130[Formula: see text]nm CMOS technology. The designed converter can extract maximum power from a TEG, without using an input capacitor ([Formula: see text] or a closed loop maximum peak power tracking circuit to regulate the input voltage ([Formula: see text]. The converter uses a low voltage oscillator coupled with charge pump to directly power the auxiliary circuits; and auxiliary circuits drives two inductors in two half cycles of a clock pulse. The measurement has been performed by using a TEG, and a voltage source (50–200[Formula: see text]mV) with a series resistance of 5[Formula: see text]ohms. The result shows that the prototype can self-starts from 70[Formula: see text]mV with 5[Formula: see text]ms startup time and can work up to a minimum of 50[Formula: see text]mV; and can extract, 57.2% (at 50[Formula: see text]mV) to 65% (at 200[Formula: see text]mV), of the available power.

Low‐voltage fully differential difference transconductance amplifier

2017 ◽  
Vol 12 (1) ◽  
pp. 73-81 ◽  
Author(s):  
Fabian Khateb ◽  
Montree Kumngern ◽  
Tomasz Kulej ◽  
Vilém Kledrowetz
Keyword(s):  
Low Voltage ◽  
Fully Differential ◽  
Transconductance Amplifier

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

scholarly journals Comparative study of symmetrical OTA performance in 180 nm, 130 nm and 90 nm CMOS technology

2019 ◽  
Vol 14 (1) ◽  
pp. 230
Author(s):  
Wan Mohammad Ehsan Aiman Bin Wan Jusoh ◽  
Siti Hawa Ruslan ◽  
Nabihah Ahmad ◽  
Warsuzarina Mat Jubadi ◽  
Rahmat Sanudin
Keyword(s):  
Comparative Study ◽  
Detection System ◽  
Cmos Technology ◽  
Common Mode ◽  
Voltage Supply ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
High Cmrr ◽  
The Comparative Study ◽  
Electrocardiogram Ecg

<span>In this paper, the comparative study of symmetrical Operational Transconductance Amplifier (OTA) performance between 180 nm, 130 nm and 90 nm CMOS technology have been done thoroughly to find the relationship between voltage supply and bias current with performance parameters (gain, power consumption and Common-Mode Rejection Ratio (CMRR)). The OTA which adopts symmetrical topology is designed carefully and simulated using Synopsys HSpice software and the results are carefully analyzed and compared. The symmetrical OTA designed in 90 nm CMOS technology is found to be the best because the power consumed is only 9.83 µW from ±0.9 V voltage supply and the OTA achieved 55.9 dB of the DC gain. The CMRR of the symmetrical 90 nm OTA is 140 dB which is sufficient to reject the common-mode signals in electrocardiogram (ECG) input signal. The symmetrical 90 nm OTA is suitable to be implemented as bioamplifier in ECG signal detection system as it consumed low power and has a high CMRR characteristic.</span>

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