Design of Current Differencing Transconductance Amplifier using a Novel Approach of Transconductance Boosting for High Frequency Applications

2019 ◽  
Vol 29 (04) ◽  
pp. 2050065
Author(s):  
Shireesh Kumar Rai ◽  
Rishikesh Pandey ◽  
Bharat Garg

This paper introduces a novel approach of transconductance boosting for current differencing transconductance amplifier (CDTA). Generally, the variation in the transconductance is achieved by changing the bias current and/or by increasing the aspect ratios of differential pair MOSFETs. These techniques of transconductance variations suffer from several serious drawbacks which include higher power dissipation, limited range of transconductance gain and lower input/output swing. The proposed approach of transconductance boosting overcomes these drawbacks at certain extent and also provides a high value of transconductance gain with acceptable range of bandwidth and power dissipation. It includes two different techniques to make it more effective for transconductance boosting. In the first technique, common source amplifiers have been used between gate and source terminals of the differential pair MOSFETs whereas in the second technique the concept of partial positive feedback is utilized. Using this approach, a new structure of CDTA namely cross-coupled common source current differencing transconductance amplifier I (CCCS-CDTA I) is proposed. To further improve the transconductance gain of CCCS-CDTA I, another structure CCCS-CDTA II is also proposed, in which the differential pair MOSFETs are replaced by two networks of “n” parallel MOSFETs having same aspect ratios. The proposed CCCS-CDTAs are simulated in Mentor Graphics Eldo simulator using TSMC 0.18[Formula: see text][Formula: see text]m process parameters. To confirm the performance of CCCS-CDTA II, physical layout and post-layout simulation results have been presented using Mentor Graphics Calibre tool. The advantages of proposed CCCS-CDTAs have also been discussed by realizing KHN filters and oscillators.

Author(s):  
B.T. Krishna ◽  
◽  
Shaik. mohaseena Salma ◽  

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.


2021 ◽  
Vol 1 (2) ◽  
pp. 1-7
Author(s):  
Krishna B.T. ◽  
mohaseena Salma Shaik.

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high-frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.


2021 ◽  
Vol 40 (1) ◽  
pp. 551-563
Author(s):  
Liqiong Lu ◽  
Dong Wu ◽  
Ziwei Tang ◽  
Yaohua Yi ◽  
Faliang Huang

This paper focuses on script identification in natural scene images. Traditional CNNs (Convolution Neural Networks) cannot solve this problem perfectly for two reasons: one is the arbitrary aspect ratios of scene images which bring much difficulty to traditional CNNs with a fixed size image as the input. And the other is that some scripts with minor differences are easily confused because they share a subset of characters with the same shapes. We propose a novel approach combing Score CNN, Attention CNN and patches. Attention CNN is utilized to determine whether a patch is a discriminative patch and calculate the contribution weight of the discriminative patch to script identification of the whole image. Score CNN uses a discriminative patch as input and predict the score of each script type. Firstly patches with the same size are extracted from the scene images. Secondly these patches are used as inputs to Score CNN and Attention CNN to train two patch-level classifiers. Finally, the results of multiple discriminative patches extracted from the same image via the above two classifiers are fused to obtain the script type of this image. Using patches with the same size as inputs to CNN can avoid the problems caused by arbitrary aspect ratios of scene images. The trained classifiers can mine discriminative patches to accurately identify some confusing scripts. The experimental results show the good performance of our approach on four public datasets.


2006 ◽  
Vol 113 ◽  
pp. 167-172
Author(s):  
Maik Mracek ◽  
Tobias Hemsel ◽  
Piotr Vasiljev ◽  
Jörg Wallaschek

Rotary ultrasonic motors have found broad industrial application in camera lens drives and other systems. Linear ultrasonic motors in contrast have only found limited applications. The main reason for the limited range of application of these very attractive devices seems to be their small force and power range. Attempts to build linear ultrasonic motors for high forces and high power applications have not been truly successful yet. To achieve drives, larger force and higher power, and multiple miniaturized motors can be combined. This approach, however, is not as simple as it appears at first glance. The electromechanical behavior of individual motors differs slightly due to manufacturing and assembly tolerances. Individual motor characteristics are strongly dependent on the driving parameters (frequency, voltage, temperature, pre-stress, etc.) and the driven load and the collective behavior of the swarm of motors is not just the linear superposition of the individual drive’s forces.


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