A Minimum-Voltage Driving Amplifier with Adaptive Three-Stage Open-Loop Gain and Folded Cascade Class-AB Output Current Control

2020 ◽  
pp. 2150145
Author(s):  
Fanyang Li ◽  
Tao Yang
Keyword(s):  
Supply Voltage ◽  
Harmonic Distortion ◽  
Open Loop ◽  
Current Control ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Loop Gain ◽  
Output Current ◽  
Class Ab ◽  
Sinusoidal Input

A driving amplifier capable of operating at a minimum voltage is proposed, aiming to subdue the distortion effect caused by large amplitude driving at the hearing aid loudspeaker. Since the linearity of a cascode amplifier usually degrades with the reduced supply voltage, a three-stage cascade amplifier having a parallel cascade second stage, and a folded cascade Class-AB output current control in place are designed. With such an arrangement, the open loop gain should still be maintained at a sufficiently high level even in the presence of increased output amplitude. Also, the minimum supply voltage required can then be reduced to merely [Formula: see text]. Fabricated on a 0.18[Formula: see text][Formula: see text]m complementary metal oxide semiconductor (CMOS) process, the proposed amplifier achieves [Formula: see text][Formula: see text]dB total harmonic distortion [Formula: see text] with a loudspeaker load of 100[Formula: see text]ohm while operating from a 1.2[Formula: see text]V supply and being subject to a 1[Formula: see text]kHz sinusoidal input.

Implementation of Single-Phase Two-Switch Midpoint Unidirectional Multilevel Converter System

2018 ◽  
Vol 19 (4) ◽  
Author(s):  
Peethala Rajiv Roy ◽  
P. Parthiban ◽  
B. Chitti Babu
Keyword(s):  
Single Phase ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Input Voltage ◽  
Open Loop ◽  
Current Control ◽  
Control Technique ◽  
Control Scheme

Abstract This paper deals with implementation of a single-phase three level converter system under low voltage condition. The frequency of the switches is made constant and involves change in ${t_{on}}$ and ${t_{off}}$ duration. For this condition the pulse width modulation control scheme for a single phase three level rectifier is developed to improve the power quality. The hysteresis current control technique is adopted to bring forth three-level PWM on the dc side of the bridge rectifier and to achieve high power factor and low harmonic distortion. Based on the proposed control scheme, the line current is driven to follow the sinusoidal current command which is in phase with the supply voltage. By using three-level voltage pattern the blocking voltage of each power device is clamped to half of the dc link voltage. The simulation and experimental results of 20W converter under low input voltage condition are shown to verify the circuit performance. Open loop simulation and hardware tests are implemented by applying a low voltage of 15 V(rms) on the input side.

scholarly journals Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 684
Author(s):  
Winai Jaikla ◽  
Sirigul Bunrueangsak ◽  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Peerawut Suwanjan ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Block Diagram ◽  
Harmonic Distortion ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Mos Transistor ◽  
Differential Input

This paper presents inductance simulators using the voltage differencing differential input buffered amplifier (VD-DIBA) as an active building block. Three types of inductance simulators, including floating lossless inductance, series inductance-resistance, and parallel inductance-resistance simulators, are proposed, in addition to their application to the 4th order elliptic lowpass ladder filter. The simple design procedures of these inductance simulators using a circuit block diagram are also given. The proposed inductance simulators employ two VD-DIBAs and two passive elements. The complementary metal oxide semiconductor (CMOS) VD-DIBA used in this design utilizes the multiple-input metal oxide semiconductor (MOS) transistor technique in order to achieve a compact and simple structure with a minimum count of transistors. Thanks to this technique, the VD-DIBA offers high performances compared to the other CMOS structures presented in the literature. The CMOS VD-DIBAs and their applications are designed and simulated in the Cadence environment using a 0.18 µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). Using a supply voltage of ±0.9 V, the linear operation of VD-DIBA is obtained over a differential input range of −0.5 V to 0.5 V. The lowpass (LP) ladder filter realized with the proposed inductance simulators shows a dynamic range (DR) of 80 dB for a total harmonic distortion (THD) of 2% at 1 kHz and a 1.8 V peak-to-peak output. In addition, the experimental results of the floating inductance simulators and their applications are obtained by using VD-DIBA constructed from the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental ones, confirming the advantages of the inductance simulators and their application.

scholarly journals High-Linearity Self-Biased CMOS Current Buffer

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 423
Author(s):  
Javier Martínez-Nieto ◽  
María Sanz-Pascual ◽  
Nicolás Medrano-Marqués ◽  
Belén Calvo-López ◽  
Arturo Sarmiento-Reyes
Keyword(s):  
High Performance ◽  
Simple Structure ◽  
Low Voltage ◽  
Harmonic Distortion ◽  
Input Resistance ◽  
Cmos Process ◽  
Output Current ◽  
Current Ratio ◽  
Class Ab ◽  
Static Power

A highly linear fully self-biased class AB current buffer designed in a standard 0.18 μ m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 μ W, features an input resistance as low as 89 Ω , high accuracy in the input–output current ratio and total harmonic distortion (THD) figures lower than −60 dB at 30 μ A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications.

Fully Differential, Bulk-Driven, Class AB, Sub-Threshold OTA With Enhanced Slew Rates and Gain

2016 ◽  
Vol 26 (01) ◽  
pp. 1750001 ◽  
Author(s):  
Tripurari Sharan ◽  
Vijaya Bhadauria
Keyword(s):  
Intrinsic Value ◽  
Harmonic Distortion ◽  
Open Loop ◽  
Cmos Process ◽  
Substrate Noise ◽  
Process Technology ◽  
Ultra Low Power ◽  
Class Ab ◽  
Fully Differential ◽  
Flipped Voltage Follower

This paper presents a single-stage ultra-low-power fully differential operational transconductance amplifier (FD-OTA) with rail-to-rail linear input range operating in weak inversion region. The input core of the OTA is comprised of source degenerated, flipped voltage follower (FVF)-based bulk-driven class AB input pair, into which a regenerative feedback loop has been inserted to boost its bulk transconductance ([Formula: see text]). The proposed FD-OTA has utilized self-cascode current mirror (SC-CM) loads, which increase its open loop gain from nominal intrinsic value of 42[Formula: see text]dB to 70.4[Formula: see text]dB. It has provided 9.24[Formula: see text]kHz gain bandwidth (GBW), consuming 64[Formula: see text]nW of quiescent power from a 0.51[Formula: see text]V single power supply at 15[Formula: see text]pF load. The proposed OTA in unity gain configuration has ensured reduced total harmonic distortion (THD) of [Formula: see text][Formula: see text]dB at 200[Formula: see text]Hz frequency and 1[Formula: see text]V[Formula: see text] signal swing. Its fully differential class AB input and output structures have ensured increased gain, GBW, slew rates and output swings with reduced nonlinearity and common mode substrate noise. The Cadence Virtuoso environment using GPDK 180[Formula: see text]nm standard [Formula: see text]-well CMOS process technology has been used to simulate the proposed circuit.

Review: Static and Dynamic Analysis Methods for Multi-Branch Biasing Circuits

2018 ◽  
Vol 27 (13) ◽  
pp. 1830008
Author(s):  
Jin Wu ◽  
Pengfei Dai ◽  
Jie Peng ◽  
Lixia Zheng ◽  
Weifeng Sun
Keyword(s):  
Feedback Loop ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Critical Parameters ◽  
Cmos Process ◽  
Stable Equilibrium Point ◽  
Static And Dynamic Analysis ◽  
Text Structures ◽  
Different Types

The fundamental theories and primary structures for the multi-branch self-biasing circuits are reviewed in this paper. First, the [Formula: see text]/[Formula: see text] and [Formula: see text]/[Formula: see text] structures illustrating the static current definition mechanism are presented, including the conditions of starting up and entering into a stable equilibrium point. Then, the AC method based on the loop gain evaluation is utilized to analyze different types of circuits. On this basis, the laws which can couple the branches of self-biasing circuits to construct a suitable close feedback loop are summarized. By adopting Taiwan Semiconductor Manufacturing Company (TSMC)’s 0.18[Formula: see text][Formula: see text]m complementary metal–oxide–semiconductor (CMOS) process with 1.8[Formula: see text][Formula: see text] supply voltage, nearly all the circuits mentioned in the paper are simulated in the same branch current condition, which is close to the corresponding calculated results. Therefore, the methods summarized in this paper can be utilized for distinguishing, constructing, and optimizing critical parameters for various structures of the self-biasing circuits.

Implementation of Coupled Inductor Based 7-level Inverter with Reduced Switches

2017 ◽  
Vol 8 (3) ◽  
pp. 1294 ◽  
Author(s):  
R. Palanisamy ◽  
K. Vijayakumar ◽  
Aishwarya Bagchi ◽  
Vachika Gupta ◽  
Swapnil Sinha
Keyword(s):  
Output Voltage ◽  
Control Algorithm ◽  
Harmonic Distortion ◽  
Current Control ◽  
Output Current ◽  
Hysteresis Current Control ◽  
Common Mode Voltage ◽  
Voltage Stress ◽  
Dsp Controller ◽  
Switching Devices

<p>This paper proposes implementation of coupled inductor based 7 level inverter with reduced number switches. The inverter which generates the sinusoidal output voltage by the use of coupled inductor with reduced total harmonic distortion. The voltage stress on each switching devices, capacitor balancing and common mode voltage can be minimized. The proposed system which gives better controlled output current and improved output voltage with diminished THD value. The switching devices of the system are controlled by using hysteresis current control algorithm by comparing the carrier signals with constant pulses with enclosed hysteresis band value. The simulation and experimental results of the proposed system outputs are verified using matlab/Simulink and TMS320F3825 dsp controller respectively.</p>

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

scholarly journals Design and Simulation Study of Active Baluns Circuits for WiMAX Applications

2019 ◽  
Vol 7 (1) ◽  
Author(s):  
Frederick Ray I. Gomez ◽  
John Richard E. Hizon ◽  
Maria Theresa G. De Leon
Keyword(s):  
Phase Difference ◽  
Simulation Study ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Cmos Process ◽  
Common Gate ◽  
Active Balun

The paper presents a design and simulation study of three active balun circuits implemented in a standard 90nm Complementary Metal-Oxide Semiconductor (CMOS) process namely: (1) common-source/drain active balun; (2) common-gate with common-source active balun; and (3) differential active balun.  The active balun designs are intended for Worldwide Interoperability for Microwave Access (WiMAX) applications operating at frequency 5.8GHz and with supply voltage of 1V.  Measurements are taken for parameters such as gain difference, phase difference, and noise figure.  All designs achieved gain difference of less than 0.23dB, phase difference of 180° ± 7.1°, and noise figure of 7.2–9.85dB, which are comparable to previous designs and researches.  Low power consumption attained at the most 4.45mW.

scholarly journals A Fully Integrated 64-Channel Recording System for Extracellular Raw Neural Signals

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2726
Author(s):  
Xiangwei Zhang ◽  
Quan Li ◽  
Chengying Chen ◽  
Yan Li ◽  
Fuqiang Zuo ◽  
...  
Keyword(s):  
Harmonic Distortion ◽  
Field Potential ◽  
Low Noise ◽  
Recording System ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Neural Signals ◽  
Fully Integrated ◽  
Rail To Rail

This paper presents a fully integrated 64-channel neural recording system for local field potential and action potential. It mainly includes 64 low-noise amplifiers, 64 programmable amplifiers and filters, 9 switched-capacitor (SC) amplifiers, and a 10-bit successive approximation register analogue-to-digital converter (SAR ADC). Two innovations have been proposed. First, a two-stage amplifier with high-gain, rail-to-rail input and output, and dynamic current enhancement improves the speed of SC amplifiers. The second is a clock logic that can be used to align the switching clock of 64 channels with the sampling clock of ADC. Implemented in an SMIC 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process, the 64-channel system chip has a die area of 4 × 4 mm2 and is packaged in a QFN−88 of 10 × 10 mm2. Supplied by 1.8 V, the total power is about 8.28 mW. For each channel, rail-to-rail electrode DC offset can be rejected, the referred-to-input noise within 1 Hz–10 kHz is about 5.5 μVrms, the common-mode rejection ratio at 50 Hz is about 69 dB, and the output total harmonic distortion is 0.53%. Measurement results also show that multiple neural signals are able to be simultaneously recorded.

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