scholarly journals Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 684
Author(s):  
Winai Jaikla ◽  
Sirigul Bunrueangsak ◽  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Peerawut Suwanjan ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Block Diagram ◽  
Harmonic Distortion ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Mos Transistor ◽  
Differential Input

This paper presents inductance simulators using the voltage differencing differential input buffered amplifier (VD-DIBA) as an active building block. Three types of inductance simulators, including floating lossless inductance, series inductance-resistance, and parallel inductance-resistance simulators, are proposed, in addition to their application to the 4th order elliptic lowpass ladder filter. The simple design procedures of these inductance simulators using a circuit block diagram are also given. The proposed inductance simulators employ two VD-DIBAs and two passive elements. The complementary metal oxide semiconductor (CMOS) VD-DIBA used in this design utilizes the multiple-input metal oxide semiconductor (MOS) transistor technique in order to achieve a compact and simple structure with a minimum count of transistors. Thanks to this technique, the VD-DIBA offers high performances compared to the other CMOS structures presented in the literature. The CMOS VD-DIBAs and their applications are designed and simulated in the Cadence environment using a 0.18 µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). Using a supply voltage of ±0.9 V, the linear operation of VD-DIBA is obtained over a differential input range of −0.5 V to 0.5 V. The lowpass (LP) ladder filter realized with the proposed inductance simulators shows a dynamic range (DR) of 80 dB for a total harmonic distortion (THD) of 2% at 1 kHz and a 1.8 V peak-to-peak output. In addition, the experimental results of the floating inductance simulators and their applications are obtained by using VD-DIBA constructed from the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental ones, confirming the advantages of the inductance simulators and their application.

scholarly journals Universal Filter Based on Compact CMOS Structure of VDDDA

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1683
Author(s):  
Winai Jaikla ◽  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Koson Pitaksuttayaprot
Keyword(s):  
Metal Oxide ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Experimental Results ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Voltage Gain ◽  
Universal Filter ◽  
Mos Transistor

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

scholarly journals A Robust 4-channel Micro-power Low-noise Neural Recording Amplifier for Hippocampal Cognitive Prosthesis

2020 ◽  
Author(s):  
Ming Ni ◽  
Yan Han ◽  
Jian Lei ◽  
Hakbong Kim
Keyword(s):  
Metal Oxide ◽  
Power Consumption ◽  
Process Variation ◽  
Neural Recording ◽  
Low Noise ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Mos Transistor ◽  
Micro Power

Abstract Background: Recording of electrical activity of neurons is indispensable for decoding the information in the brain. The amplitude of signals recorded by electrodes is small, and it must be amplified to the level that can be digitalized by the analog-to-digital convert (ADC). A micro-power low-noise neural recording amplifier is indispensable for implant hippocampal cognitive prosthesis. When the process turns into deep submicron, the gate leakage current of the metal oxide semiconductor (MOS) transistor becomes larger and mismatch between devices becomes worsen. It is necessary to keep the neural amplifier robust in all process corners. Methods: The proposed circuit is a two-stage amplifier which can achieve a good trade-off between power consumption and noise. Four second-stage amplifiers share a common reference amplifier to reduce area and power consumption. A pseudo-resistor with high resistance is utilized to realize a very-low frequency high pass corner without external components. In order to minimize process variation, a bulk-compensated (BC) technique is adopted to maintain adequate tolerance in all corner case. Results: The 4-channel neural amplifier is designed and fabricated in a 40 nm standard complementary metal oxide semiconductor (CMOS) process. It achieves a mid-band gain of 54 dB, a bandwidth of 70 Hz to 7.7 kHz, a total input-referred noise of 3.2 μVrms , and a Noise Efficiency Factor (NEF) of 3.3 while consuming 4.68 µW from the 1.1 V supply. The core area of one channel is only 0.032 mm 2 . Conclusion: A 4-channel integrated neural recording amplifier chip with bias-compensated circuits is presented in this paper. Extensive simulations insure that the design is “center”. The chip layout is verified using design rules check (DRC) and layout versus schematic (LVS) design check with the help of verification tools. Test results shows that it is less sensitive to process variation and consumes less power compared with amplifier without bulk-compensated circuit. This makes the design robust and uniquely appropriate for low-power implant application.

scholarly journals MOSFET ZTC Condition Analysis for a Self-biased Current Reference Design

2015 ◽  
Vol 10 (2) ◽  
pp. 103-112
Author(s):  
Pedro Toledo ◽  
Hamilton Klimach ◽  
David Cordova ◽  
Sergio Bampi ◽  
Eric Fabris
Keyword(s):  
Metal Oxide ◽  
Temperature Coefficient ◽  
Supply Voltage ◽  
Metal Oxide Semiconductor ◽  
Fabrication Process ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Silicon Area ◽  
Current Reference ◽  
Strong Inversion

In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be implemented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and provides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, showing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/oC from -40 to +85oC, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V.

Power performance of 65 nm CMOS integrated LDMOS transistors at WLAN and X-band frequencies

2015 ◽  
Vol 8 (2) ◽  
pp. 135-141
Author(s):  
Sara Lotfi ◽  
Olof Bengtsson ◽  
Jörgen Olsson
Keyword(s):  
Metal Oxide ◽  
Power Density ◽  
Output Power ◽  
Supply Voltage ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Area Network ◽  
Power Added Efficiency ◽  
X Band

Laterally diffused metal oxide semiconductor (LDMOS) transistors with 10 V breakdown voltage have been implemented in a 65 nm Complementary metal oxide semiconductor (CMOS) process without extra masks or process steps. Radio frequency (RF) performance for Wireless local area network (WLAN) frequencies and in X-band at 8 GHz is investigated by load-pull measurements in class AB operation for both 3.3 and 5 V supply voltage. Results at 2.45 GHz showed 290 mW/mm output power density with 17 dB linear gain and over 45% power added efficiency (PAE) at 4 dB compression at a supply voltage of 5 V. Furthermore, results in X-band at 8 GHz show 8 dB linear gain, 320 mW/mm output power density and over 22% PAE at 4 dB compression. Third-order intermodulation measurements at 8 GHz revealed OIP3 of 18.9 and 21.9 dBm at 3.3 and 5 V, respectively. The transistors were also tested for reliability which showed no drift in quiescent current after 26 h of DC stress while high-power RF stress showed only small extrapolated drift at 10 years in output power density. This is to the authors' knowledge the first time high output power density in X-band is demonstrated for integrated LDMOS transistors manufactured in a 65 nm CMOS process without extra process steps.

scholarly journals A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes

Sensors ◽  
2019 ◽  
Vol 19 (19) ◽  
pp. 4149
Author(s):  
Xiang Li ◽  
Rui Li ◽  
Chunge Ju ◽  
Bo Hou ◽  
Qi Wei ◽  
...  
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Output Voltage ◽  
Charge Pump ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Temperature Changes ◽  
Adjustable Range

Micromachined gyroscopes require high voltage (HV) for actuation and detection to improve its precision, but the deviation of the HV caused by temperature fluctuations will degrade the sensor’s performance. In this paper, a high-voltage temperature-insensitive charge pump is proposed. Without adopting BCD (bipolar-CMOS-DMOS) technology, the output voltage can be boosted over the breakdown voltage of n-well/substrate diode using triple-well NMOS (n-type metal-oxide-semiconductor) transistors. By controlling the pumping clock’s amplitude continuously, closed-loop regulation is realized to reduce the output voltage’s sensitivity to temperature changes. Besides, the output level is programmable linearly in a large range by changing the reference voltage. The whole circuit has been fabricated in a 0.18- μ m standard CMOS (complementary metal-oxide-semiconductor) process with a total area of 2.53 mm 2 . Measurements indicate that its output voltage has a linear adjustable range from around 13 V to 16.95 V, and temperature tests show that the maximum variations of the output voltage at − 40 ∼ 80 ∘ C are less than 1.1%.

scholarly journals Magnetic Micro Sensors with Two Magnetic Field Effect Transistors Fabricated Using the Commercial Complementary Metal Oxide Semiconductor Process

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4731
Author(s):  
Wei-Ren Chen ◽  
Yao-Chuan Tsai ◽  
Po-Jen Shih ◽  
Cheng-Chih Hsu ◽  
Ching-Liang Dai
Keyword(s):  
Magnetic Field ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Magnetic Field Effect ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Micro Sensor

The fabrication and characterization of a magnetic micro sensor (MMS) with two magnetic field effect transistors (MAGFETs) based on the commercial complementary metal oxide semiconductor (CMOS) process are investigated. The magnetic micro sensor is a three-axis sensing type. The structure of the magnetic microsensor is composed of an x/y-MAGFET and a z-MAGFET. The x/y-MAGFET is employed to sense the magnetic field (MF) in the x- and y-axis, and the z-MAGFET is used to detect the MF in the z-axis. To increase the sensitivity of the magnetic microsensor, gates are introduced into the two MAGFETs. The sensing current of the MAGFET enhances when a bias voltage is applied to the gates. The finite element method software Sentaurus TCAD was used to analyze the MMS’s performance. Experiments show that the MMS has a sensitivity of 182 mV/T in the x-axis MF and a sensitivity of 180 mV/T in the y-axis MF. The sensitivity of the MMS is 27.8 mV/T in the z-axis MF.

A Very Low Dark Current Temperature-Resistant, Wide Dynamic Range, Complementary Metal Oxide Semiconductor Image Sensor

2008 ◽  
Vol 47 (7) ◽  
pp. 5390-5395 ◽  
Author(s):  
Koichi Mizobuchi ◽  
Satoru Adachi ◽  
Jose Tejada ◽  
Hiromichi Oshikubo ◽  
Nana Akahane ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Dark Current ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Image Sensor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Wide Dynamic Range

High Sensitivity Dynamic Range Enhanced Complementary Metal–Oxide–Semiconductor Imager with Noise Suppression

2008 ◽  
Vol 47 (4) ◽  
pp. 2761-2766
Author(s):  
Satoru Adachi ◽  
Woonghee Lee ◽  
Nana Akahane ◽  
Hiromichi Oshikubo ◽  
Koichi Mizobuchi ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Noise Suppression ◽  
Dynamic Range ◽  
High Sensitivity ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor
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