Numerical Study on SEU Performance of Strain Engineered 6T-SRAM Cells

2021 ◽  
pp. 2250034
Author(s):  
N. Vinodhkumar ◽  
G. Durga ◽  
S. Muthumanickam
Keyword(s):  
Field Effect Transistor ◽  
Numerical Study ◽  
Metal Oxide Semiconductor ◽  
Soft Error ◽  
Oxide Semiconductor ◽  
Error Performance ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Effect Transistor ◽  
The Impact

In this work, the impact of shallow trench isolation (STI) and dual stress liner (DSL) -induced stresses on soft error performance of 30-nm gate length Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET)-based 6T-SRAM cells is studied using process and device simulations. Under nine different stress combinations, i.e., nine different SRAMs, our simulation results show that the stresses introduced from STI and DSL enhance the soft error performance of the cells significantly.

Effect of Metal - Silicon Nanowire Contacts on the Performance of Accumulation Metal Oxide Semiconductor Field Effect Transistor

2008 ◽  
Vol 1144 ◽  
Author(s):  
Pranav Garg ◽  
Yi Hong ◽  
Md. Mash-Hud Iqbal ◽  
Stephen J. Fonash
Keyword(s):  
Metal Oxide ◽  
Silicon Nanowires ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Silicon Nanowire ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Manufacturing Cost ◽  
Effect Transistor ◽  
The Impact

ABSTRACTRecently, we have experimentally demonstrated a very simply structured unipolar accumulation-type metal oxide semiconductor field effect transistor (AMOSFET) using grow-in-place silicon nanowires. The AMOSFET consists of a single doping type nanowire, metal source and drain contacts which are separated by a partially gated region. Despite its simple configuration, it is capable of high performance thereby offering the potential of a low manufacturing-cost transistor. Since the quality of the metal/semiconductor ohmic source and drain contacts impacts AMOSFET performance, we repot here on initial exploration of contact variations and of the impact of thermal process history. With process optimization, current on/off ratios of 106 and subthreshold swings of 70 mV/dec have been achieved with these simple devices

Avalanche Ruggedness Assessment of 1.2kV 45mΩ Asymmetric Trench SiC MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 837-842
Author(s):  
Xiao Chuan Deng ◽  
Hao Zhu ◽  
Xuan Li ◽  
Xiao Jie Xu ◽  
Kun Zhou ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Single Pulse ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Safe Operation ◽  
Effect Transistor ◽  
The Impact

In this paper, avalanche ruggedness of the commercial 1.2kV 45mΩ asymmetric silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) is investigated by single-pulse unclamped inductive switching (UIS) test. The avalanche safe operation area (SOA) of the MOSFET is established. The impact of inductance and temperature on avalanche capability is exhibited, which is valuable for many application circuits. The variation in critical avalanche energy with peak avalanche current, peak avalanche current with avalanche time, and temperatures dependence of critical avalanche energy are confirmed.

scholarly journals Impact of the Stress on the Sub-Micron N-Metal Oxide Semiconductor Field Effect Transistor Characteristics

2001 ◽  
Vol 24 (3) ◽  
pp. 187-199 ◽  
Author(s):  
R. Marrakh ◽  
A. Bouhdada
Keyword(s):  
Field Effect Transistor ◽  
Current Model ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
Interface Charge ◽  
Effect Transistor ◽  
Spatio Temporal ◽  
The Impact

In this paper, we present a drain current model for stressed short-channel MOSFET's. Stress conditions are chosen so that the interface states generated by hot-carriers are dominant. The defects generated during stress time are simulated by a spatio-temporal gaussian distribution. The parasitic source and drain resistances are included. We also investigate the impact of the interface charge density, generated during stress, on the transconductance. Simulation results show a significant degradation of the drain current versus stress time.

Shielded Gate SiC Trench Power MOSFET with Ultra-Low Switching Loss

2018 ◽  
Vol 924 ◽  
pp. 765-769
Author(s):  
Xuan Li ◽  
Xing Tong ◽  
Alex Q. Huang ◽  
Shi Qiu ◽  
Xu She ◽  
...  
Keyword(s):  
Figure Of Merit ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Switching Loss ◽  
Device Structure ◽  
Switching Speed ◽  
Effect Transistor ◽  
High Switching Speed ◽  
The Impact

A shielded gate trench silicon carbide (SiC) metal oxide semiconductor field effect transistor (SG-TMOS) is proposed and investigated by simulation in this paper. The impact of shielded gate design in SG-TMOS on Miller charge (Qgd) as well as conduction resistance (Ron) are comprehensively discussed, showing a tradeoff between Qgdand Ron. Furthermore, the Huang’s Figure of Merit (HFOM) of the SG-TMOS with reasonable design of SG is reduced more than 20%, compared with the conventional trench MOSFET (C-TMOS). Therefore, the proposed SG-TMOS is a competitive next generation device structure for ultra-high switching speed SiC MOSFET.

scholarly journals Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization

Materials ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2316
Author(s):  
Kalparupa Mukherjee ◽  
Carlo De Santi ◽  
Matteo Borga ◽  
Karen Geens ◽  
Shuzhen You ◽  
...  
Keyword(s):  
Field Effect Transistor ◽  
Dynamic Performance ◽  
Power Conversion ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Current Analysis ◽  
Power Transistors ◽  
Trench Structure ◽  
Effect Transistor ◽  
Gan On Si

The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

scholarly journals 4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

Materials ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3554
Author(s):  
Jaeyeop Na ◽  
Jinhee Cheon ◽  
Kwangsoo Kim
Keyword(s):  
Dynamic Characteristics ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Switching Loss ◽  
Switching Speed ◽  
Polysilicon Gate ◽  
Effect Transistor ◽  
Switching Characteristics

In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.

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