Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement

Author(s):  
Chin-Long Wey ◽  
M. A. Khalil ◽  
Jim Liu ◽  
Gregory Wierzba
2015 ◽  
Vol 821-823 ◽  
pp. 741-744
Author(s):  
Toru Hiyoshi ◽  
Takeyoshi Masuda ◽  
Yu Saitoh ◽  
Keiji Wada ◽  
Takashi Tsuno ◽  
...  

The authors reported the DMOSFETs fabricated on the 4H-SiC(0-33-8) in ECSCRM2012 and the novel V-groove MOSFETs, having (0-33-8) on the trench sidewall in ICSCRM2013. In this paper, we applied both the thick bottom oxide and the buried p+ regions to the V-groove MOSFETs for the protection of the trench bottom oxide. The V-groove MOSFET showed the low specific on-resistance of 3.2 mΩcm2 and the high blocking voltage of 1700 V on the bounty of the high channel mobility and the gate oxide protection, respectively. We also tested the gate oxide reliability of the V-groove MOSFET by constant-voltage stress TDDB measurement. The charge-to-breakdown was 18.0 C/cm2 at room temperature and 4.4 C/cm2 at 145°C. In addition, the stability of the threshold voltage was characterized with the VMOSFETs.


1995 ◽  
Vol 35 (3) ◽  
pp. 603-608 ◽  
Author(s):  
S.R. Anderson ◽  
R.D. Schrimpf ◽  
K.F. Galloway ◽  
J.L. Titus

1998 ◽  
Vol 38 (2) ◽  
pp. 255-258 ◽  
Author(s):  
G Ghidini ◽  
C Clementi ◽  
D Drera ◽  
F Maugain

2021 ◽  
Author(s):  
Tianshi Liu ◽  
Shengnan Zhu ◽  
Michael Jin ◽  
Limeng Shi ◽  
Marvin H. White ◽  
...  

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