Gate Oxide Reliability of 4H-SiC V-Groove Trench MOSFET with Thick Bottom Oxide

2015 ◽  
Vol 821-823 ◽  
pp. 741-744
Author(s):  
Toru Hiyoshi ◽  
Takeyoshi Masuda ◽  
Yu Saitoh ◽  
Keiji Wada ◽  
Takashi Tsuno ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Gate Oxide ◽  
The Novel ◽  
Constant Voltage ◽  
Channel Mobility ◽  
Oxide Reliability ◽  
Blocking Voltage ◽  
Voltage Stress ◽  
The Stability

The authors reported the DMOSFETs fabricated on the 4H-SiC(0-33-8) in ECSCRM2012 and the novel V-groove MOSFETs, having (0-33-8) on the trench sidewall in ICSCRM2013. In this paper, we applied both the thick bottom oxide and the buried p+ regions to the V-groove MOSFETs for the protection of the trench bottom oxide. The V-groove MOSFET showed the low specific on-resistance of 3.2 mΩcm2 and the high blocking voltage of 1700 V on the bounty of the high channel mobility and the gate oxide protection, respectively. We also tested the gate oxide reliability of the V-groove MOSFET by constant-voltage stress TDDB measurement. The charge-to-breakdown was 18.0 C/cm2 at room temperature and 4.4 C/cm2 at 145°C. In addition, the stability of the threshold voltage was characterized with the VMOSFETs.

3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide

2011 ◽  
Vol 679-680 ◽  
pp. 645-648 ◽  
Author(s):  
Motoki Kobayashi ◽  
Hidetsugu Uchida ◽  
Akiyuki Minami ◽  
Toyokazu Sakata ◽  
Romain Esteve ◽  
...  
Keyword(s):  
Titanium Nitride ◽  
High Performance ◽  
Room Temperature ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Mobility ◽  
Thermally Grown Oxides ◽  
Metal Gates ◽  
Blocking Voltage ◽  
Gate Oxide Integrity

3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

9 kV 4H-SiC IGBTs with 88 mΩ·cm2 of R diff, on

2007 ◽  
Vol 556-557 ◽  
pp. 771-774 ◽  
Author(s):  
Qing Chun Jon Zhang ◽  
Charlotte Jonas ◽  
Bradley Heath ◽  
Mrinal K. Das ◽  
Sei Hyung Ryu ◽  
...  
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
High Power ◽  
Room Temperature ◽  
Elevated Temperatures ◽  
Gate Bias ◽  
Channel Mobility ◽  
Fast Switching ◽  
Blocking Voltage ◽  
First Time

SiC IGBTs are suitable for high power, high temperature applications. For the first time, the design and fabrication of 9 kV planar p-IGBTs on 4H-SiC are reported in this paper. A differential on-resistance of ~ 88 m(cm2 at a gate bias of –20 V is achieved at 25°C, and decreases to ~24.8 m(cm2 at 200°C. The device exhibits a blocking voltage of 9 kV with a leakage current density of 0.1 mA/cm2. The hole channel mobility is 6.5 cm2/V-s at room temperature with a threshold voltage of –6.5 V resulting in enhanced conduction capability. Inductive switching tests have shown that IGBTs feature fast switching capability at both room and elevated temperatures.

Reliability and Ruggedness of Planar Silicon Carbide MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 782-787
Author(s):  
Kevin Matocha ◽  
In Hwan Ji ◽  
Sauvik Chowdhury
Keyword(s):  
Silicon Carbide ◽  
Threshold Voltage ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Time Dependent ◽  
Gate Bias ◽  
Constant Voltage ◽  
Time Dependent Dielectric Breakdown ◽  
Planar Silicon ◽  
State Of Art

The reliability and ruggedness of Monolith/Littelfuse planar SiC MOSFETs have been evaluated using constant voltage time-dependent dielectric breakdown for gate oxide wearout predictions, showing estimated > 100 year life at VGS=+25V and T=175C. Using extended time high-temperature gate bias, we have shown < 250 mV threshold voltage shifts for > 5000 hours under VGS=+25V and negligible threshold voltage shifts for > 2500 hours under VGS=-10V, both at T=175C. Under unclamped inductive switching, these 1200V, 80 mOhm SiC MOSFETs survive 1000 mJ of avalanche energy, meeting state-of-art ruggedness for 1200V SiC MOSFETs.

Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry

2018 ◽  
Vol 924 ◽  
pp. 697-702 ◽  
Author(s):  
Sauvik Chowdhury ◽  
Levi Gant ◽  
Blake Powell ◽  
Kasturirangan Rangaswamy ◽  
Kevin Matocha
Keyword(s):  
Room Temperature ◽  
Stress Testing ◽  
Short Circuit ◽  
Gate Oxide ◽  
High Volume ◽  
Inductive Load ◽  
Switching Losses ◽  
Oxide Reliability ◽  
Silicon Cmos

This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm2 at room temperature, increasing to 7.5 mΩ.cm2 at 175 °C. Total switching losses were less than 300μJ (VDD = 800V, ID = 20A). The devices showed excellent gate oxide reliability with VTH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (VGS = 25V) and 2500 hours (VGS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.

Effects of N2O Anneal on Channel Mobility of 4H-SiC MOSFET and Gate Oxide Reliability

2005 ◽  
Vol 483-485 ◽  
pp. 697-700 ◽  
Author(s):  
Keiko Fujihira ◽  
Yoichiro Tarui ◽  
Kenichi Ohtsuka ◽  
Masayuki Imaizumi ◽  
Tetsuya Takami
Keyword(s):  
Field Effect ◽  
Gate Oxide ◽  
Field Effect Mobility ◽  
Channel Mobility ◽  
Oxide Reliability ◽  
Anneal Temperature

The effect of N2O anneal on channel mobility of inversion-type 4H-SiC n-channel MOSFET has been systematically investigated. It is found that the mobility increases with increasing anneal temperature from 900 to 1150°C. The highest field effect mobility of 30 cm2/Vs is achieved by 1150°C anneal for 3 h, which is about 20 times higher than that for non-annealed MOSFET. In order to investigate the oxide reliability, TDDB measurement has been performed on SiO2 grown on n-type 4H-SiC. The oxide lifetime is found to be drastically improved by N2O anneal.

Effects of N2O Anneal on Channel Mobility of 4H-SiC MOSFET and Gate Oxide Reliability

2005 ◽  
pp. 697-700
Author(s):  
Keiko Fujihira ◽  
Yoichiro Tarui ◽  
Ken Ichi Ohtsuka ◽  
Masayuki Imaizumi ◽  
Tetsuya Takami
Keyword(s):  
Gate Oxide ◽  
Channel Mobility ◽  
Oxide Reliability

4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal

2006 ◽  
Vol 527-529 ◽  
pp. 1265-1268 ◽  
Author(s):  
Jeffery B. Fedison ◽  
Chris S. Cowen ◽  
Jerome L. Garrett ◽  
E.T. Downey ◽  
James W. Kretchmer ◽  
...  
Keyword(s):  
Atomic Force Microscopy ◽  
High Temperature ◽  
Room Temperature ◽  
Gate Oxide ◽  
Surface Roughening ◽  
Force Microscopy ◽  
Atomic Force ◽  
N Source ◽  
High Temperature Anneal ◽  
Blocking Voltage

Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).

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