High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability

In this paper, a high-accuracy programmable timing generator with wide-range tuning capability is proposed. With the aid of dual delay-locked loop (DLL), both of the coarse- and fine-tuning mechanisms are operated in precise closed-loop scheme to lessen the effects of the ambient variations. The timing generator can provide sub-gate resolution and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.18 μm 1P6M technology. The test chip area occupies 1.9 mm2. The reference clock cycle can be divided into 128 bins by interpolation to obtain 14 ps resolution with the clock rate at 550 MHz. The INL and DNL are within −0.21~+0.78 and −0.27~+0.43 LSB, respectively.

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A Novel Ultrasonic TOF Ranging System Using AlN Based PMUTs

Micromachines ◽

10.3390/mi12030284 ◽

2021 ◽

Vol 12 (3) ◽

pp. 284

Author(s):

Yihsiang Chiu ◽

Chen Wang ◽

Dan Gong ◽

Nan Li ◽

Shenglin Ma ◽

...

Keyword(s):

Clock Cycle ◽

High Accuracy ◽

Ultrasonic Waves ◽

Oxide Semiconductor ◽

Average Error ◽

Cmos Process ◽

Clock Frequency ◽

Time Frequency ◽

Range Finding ◽

Wide Range

This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.

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A wide-range delay-locked loop with a fixed latency of one clock cycle

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2002.800922 ◽

2002 ◽

Vol 37 (8) ◽

pp. 1021-1027 ◽

Cited By ~ 111

Author(s):

Hsiang-Hui Chang ◽

Jyh-Woei Lin ◽

Ching-Yuan Yang ◽

Shen-Iuan Liu

Keyword(s):

Clock Cycle ◽

Delay Locked Loop ◽

Wide Range

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A 0.0052 mm2 COMPACT DIGITAL PLL IN 65 nm CMOS

Journal of Circuits System and Computers ◽

10.1142/s0218126612400269 ◽

2012 ◽

Vol 21 (08) ◽

pp. 1240026 ◽

Cited By ~ 1

Author(s):

ZHIHONG LUO ◽

YEUNG ON AU ◽

BENJAMIN LAU ◽

HENRY LAW

Keyword(s):

Clock Cycle ◽

Cell Number ◽

Ring Oscillator ◽

Total Power ◽

Nand Gate ◽

Clock Frequency ◽

Clock Jitter ◽

Delay Cell ◽

Wide Range ◽

Reference Clock

A novel structure of digital phase locked loop (PLL) is presented in this paper. It uses digitally controlled oscillator (DCO) to generate the clock. At the beginning of each reference clock cycle, the DCO is fully reset and restarts to oscillate to prevent the long term jitter accumulation and increase the loop stability. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and in cycle load adjust to digitally control the DCO output clock frequency, in order to get wider frequency range and smaller jitter. This digital PLL uses NAND gate as the basic delay cell of ring oscillator, which can completely reset DCO in a very short time. It uses binary search to achieve fast lock and uses shift chain to get better input clock jitter tolerance. This digital PLL has been silicon validated in GLOBALFOUNDRIES 65 nm Generic process. Its chip area is only 0.0052 mm2. In typical condition, DCO's frequency has a wide range between 550 MHz and 2.45 GHz. Its total power is around 1.4 mW when DCO's frequency is 1.8 GHz. This PLL can be locked very fast in 25 divided reference clock cycles, and its output clock jitter is around 18 ps.

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A wide-range and fixed latency of one clock cycle delay-locked loop

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) ◽

10.1109/iscas.2002.1010314 ◽

2003 ◽

Author(s):

Hsiang-Hui Chang ◽

Jyh-Woei Lin ◽

Shen-Iuan Liu

Keyword(s):

Clock Cycle ◽

Delay Locked Loop ◽

Wide Range

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Evaluation of Optimal Vibrotactile Feedback for Force-Controlled Upper Limb Myoelectric Prostheses

Sensors ◽

10.3390/s19235209 ◽

2019 ◽

Vol 19 (23) ◽

pp. 5209 ◽

Cited By ~ 1

Author(s):

Andrea Gonzalez-Rodriguez ◽

Jose L. Ramon ◽

Vicente Morell ◽

Gabriel J. Garcia ◽

Jorge Pomares ◽

...

Keyword(s):

Real Time ◽

Upper Limb ◽

Closed Loop ◽

Fine Tuning ◽

Vibrotactile Feedback ◽

Loop Control ◽

Myoelectric Prostheses ◽

Amplitude Level ◽

Real Time Application ◽

Selection Of

The main goal of this study is to evaluate how to optimally select the best vibrotactile pattern to be used in a closed loop control of upper limb myoelectric prostheses as a feedback of the exerted force. To that end, we assessed both the selection of actuation patterns and the effects of the selection of frequency and amplitude parameters to discriminate between different feedback levels. A single vibrotactile actuator has been used to deliver the vibrations to subjects participating in the experiments. The results show no difference between pattern shapes in terms of feedback perception. Similarly, changes in amplitude level do not reflect significant improvement compared to changes in frequency. However, decreasing the number of feedback levels increases the accuracy of feedback perception and subject-specific variations are high for particular participants, showing that a fine-tuning of the parameters is necessary in a real-time application to upper limb prosthetics. In future works, the effects of training, location, and number of actuators will be assessed. This optimized selection will be tested in a real-time proportional myocontrol of a prosthetic hand.

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Harnessing methylation and AdoMet-utilising enzymes for selective modification in cascade reactions

Organic & Biomolecular Chemistry ◽

10.1039/d1ob00354b ◽

2021 ◽

Author(s):

Freideriki Michailidou ◽

Andrea Rentmeister

Keyword(s):

Natural Products ◽

Small Molecules ◽

Cascade Reactions ◽

Fine Tuning ◽

Wide Range

Enzyme-mediated methylation is a very important reaction in nature, yielding a wide range of modified natural products, diversifying small molecules and fine-tuning the activity of biomacromolecules. The field has attracted...

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Suppressing meta-holographic artifacts by laser coherence tuning

Light Science & Applications ◽

10.1038/s41377-021-00547-0 ◽

2021 ◽

Vol 10 (1) ◽

Author(s):

Yaniv Eliezer ◽

Geyang Qu ◽

Wenhong Yang ◽

Yujie Wang ◽

Hasan Yılmaz ◽

...

Keyword(s):

Spatial Coherence ◽

Fine Tuning ◽

Total Power ◽

Image Sharpness ◽

Continuous Tuning ◽

Fine Spatial Resolution ◽

Compact Size ◽

Wide Range ◽

Fabrication Defects ◽

Holographic Displays

AbstractA metasurface hologram combines fine spatial resolution and large viewing angles with a planar form factor and compact size. However, it suffers coherent artifacts originating from electromagnetic cross-talk between closely packed meta-atoms and fabrication defects of nanoscale features. Here, we introduce an efficient method to suppress all artifacts by fine-tuning the spatial coherence of illumination. Our method is implemented with a degenerate cavity laser, which allows a precise and continuous tuning of the spatial coherence over a wide range, with little variation in the emission spectrum and total power. We find the optimal degree of spatial coherence to suppress the coherent artifacts of a meta-hologram while maintaining the image sharpness. This work paves the way to compact and dynamical holographic displays free of coherent defects.

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A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

Electronics ◽

10.3390/electronics10020177 ◽

2021 ◽

Vol 10 (2) ◽

pp. 177

Author(s):

Dongjun Park ◽

Sungwook Choi ◽

Jongsun Kim

Keyword(s):

Sampling Technique ◽

Cmos Process ◽

Detection Range ◽

Delay Locked Loop ◽

Delta Sigma Modulator ◽

Correlated Double Sampling ◽

Delta Sigma ◽

Fast Power ◽

Low Jitter ◽

Reference Clock

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

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Micro Flat End Milling Simulation Model With Instantaneous Plowing Area Prediction

Journal of Micro and Nano-Manufacturing ◽

10.1115/1.4032757 ◽

2016 ◽

Vol 4 (2) ◽

Author(s):

Abdolreza Bayesteh ◽

Junghyuk Ko ◽

Martin Byung-Guk Jun

Keyword(s):

Feed Rate ◽

Tool Path ◽

End Milling ◽

Chip Thickness ◽

Depth Of Cut ◽

Uncut Chip Thickness ◽

Chip Area ◽

Edge Radius ◽

Wide Range ◽

Radial Depth

There is an increasing demand for product miniaturization and parts with features as low as few microns. Micromilling is one of the promising methods to fabricate miniature parts in a wide range of sectors including biomedical, electronic, and aerospace. Due to the large edge radius relative to uncut chip thickness, plowing is a dominant cutting mechanism in micromilling for low feed rates and has adverse effects on the surface quality, and thus, for a given tool path, it is important to be able to predict the amount of plowing. This paper presents a new method to calculate plowing volume for a given tool path in micromilling. For an incremental feed rate movement of a micro end mill along a given tool path, the uncut chip thickness at a given feed rate is determined, and based on the minimum chip thickness value compared to the uncut chip thickness, the areas of plowing and shearing are calculated. The workpiece is represented by a dual-Dexel model, and the simulation properties are initialized with real cutting parameters. During real-time simulation, the plowed volume is calculated using the algorithm developed. The simulated chip area results are qualitatively compared with measured resultant forces for verification of the model and using the model, effects of cutting conditions such as feed rate, edge radius, and radial depth of cut on the amount of shearing and plowing are investigated.

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