A 0.0052 mm2 COMPACT DIGITAL PLL IN 65 nm CMOS

2012 ◽  
Vol 21 (08) ◽  
pp. 1240026 ◽  
Author(s):  
ZHIHONG LUO ◽  
YEUNG ON AU ◽  
BENJAMIN LAU ◽  
HENRY LAW
Keyword(s):  
Clock Cycle ◽  
Cell Number ◽  
Ring Oscillator ◽  
Total Power ◽  
Nand Gate ◽  
Clock Frequency ◽  
Clock Jitter ◽  
Delay Cell ◽  
Wide Range ◽  
Reference Clock

A novel structure of digital phase locked loop (PLL) is presented in this paper. It uses digitally controlled oscillator (DCO) to generate the clock. At the beginning of each reference clock cycle, the DCO is fully reset and restarts to oscillate to prevent the long term jitter accumulation and increase the loop stability. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and in cycle load adjust to digitally control the DCO output clock frequency, in order to get wider frequency range and smaller jitter. This digital PLL uses NAND gate as the basic delay cell of ring oscillator, which can completely reset DCO in a very short time. It uses binary search to achieve fast lock and uses shift chain to get better input clock jitter tolerance. This digital PLL has been silicon validated in GLOBALFOUNDRIES 65 nm Generic process. Its chip area is only 0.0052 mm2. In typical condition, DCO's frequency has a wide range between 550 MHz and 2.45 GHz. Its total power is around 1.4 mW when DCO's frequency is 1.8 GHz. This PLL can be locked very fast in 25 divided reference clock cycles, and its output clock jitter is around 18 ps.

scholarly journals A Novel Ultrasonic TOF Ranging System Using AlN Based PMUTs

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 284
Author(s):  
Yihsiang Chiu ◽  
Chen Wang ◽  
Dan Gong ◽  
Nan Li ◽  
Shenglin Ma ◽  
...  
Keyword(s):  
Clock Cycle ◽  
High Accuracy ◽  
Ultrasonic Waves ◽  
Oxide Semiconductor ◽  
Average Error ◽  
Cmos Process ◽  
Clock Frequency ◽  
Time Frequency ◽  
Range Finding ◽  
Wide Range

This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.

In-Situ Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA

2019 ◽  
Vol 29 (06) ◽  
pp. 2050098
Author(s):  
Minh Tung Dam ◽  
Van Toan Nguyen ◽  
Jeong-Gun Lee
Keyword(s):  
High Speed ◽  
Clock Cycle ◽  
Ring Oscillator ◽  
Target System ◽  
Clock Frequency ◽  
Frequency Scaling ◽  
Timing Error ◽  
Functional Correctness ◽  
Dynamic Frequency

In this paper, a timing error predictor (TEP) for adaptive frequency scaling (AFS) is proposed on a field-programmable gate array (FPGA). The use of TEP-based AFS can minimize large timing margin which is added to a clock cycle time for tolerating process, voltage, and temperature (PVT) variations. On an FPGA, in general, the typical dynamic frequency scaling has used the feature of dynamic frequency synthesis (DFS) in a digital clock manager (DCM). However, it has a long locking time. Moreover, during the DCM reconfiguration for generating a new frequency, the lock signal of the DCM can be lost and it leads to possible glitches or spikes at the output. In this work, a variable-length ring oscillator (VLRO), which employs a high-speed carry chain in an FPGA, is proposed to replace the DCM for changing the frequency within one clock cycle without introducing any glitches. Furthermore, an in-situ TEP, which detects timing errors, is combined with VLRO to further reduce the timing margin of a target system. Our proposed in-situ TEP-based AFS scheme is applied to a [Formula: see text]-bit multiplier and implemented on a Spartan-6 FPGA device (XFC6SLX45). The functional correctness of the TEP is verified under various DC supply voltages and operating frequencies. The experimental results show that the proposed TEP-based AFS system switches the clock frequency correctly within two clock cycles and improves circuit performance up to [Formula: see text] the nominal operating condition by minimizing the timing margin.

scholarly journals High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Ting-Li Chu ◽  
Sin-Hong Yu ◽  
Chorng-Sii Hwang
Keyword(s):  
Closed Loop ◽  
Clock Cycle ◽  
High Accuracy ◽  
Fine Tuning ◽  
Chip Area ◽  
Delay Locked Loop ◽  
Wide Range ◽  
Instantaneous Switching ◽  
Loop Scheme ◽  
Reference Clock

In this paper, a high-accuracy programmable timing generator with wide-range tuning capability is proposed. With the aid of dual delay-locked loop (DLL), both of the coarse- and fine-tuning mechanisms are operated in precise closed-loop scheme to lessen the effects of the ambient variations. The timing generator can provide sub-gate resolution and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.18 μm 1P6M technology. The test chip area occupies 1.9 mm2. The reference clock cycle can be divided into 128 bins by interpolation to obtain 14 ps resolution with the clock rate at 550 MHz. The INL and DNL are within −0.21~+0.78 and −0.27~+0.43 LSB, respectively.

scholarly journals Suppressing meta-holographic artifacts by laser coherence tuning

2021 ◽  
Vol 10 (1) ◽  
Author(s):  
Yaniv Eliezer ◽  
Geyang Qu ◽  
Wenhong Yang ◽  
Yujie Wang ◽  
Hasan Yılmaz ◽  
...  
Keyword(s):  
Spatial Coherence ◽  
Fine Tuning ◽  
Total Power ◽  
Image Sharpness ◽  
Continuous Tuning ◽  
Fine Spatial Resolution ◽  
Compact Size ◽  
Wide Range ◽  
Fabrication Defects ◽  
Holographic Displays

AbstractA metasurface hologram combines fine spatial resolution and large viewing angles with a planar form factor and compact size. However, it suffers coherent artifacts originating from electromagnetic cross-talk between closely packed meta-atoms and fabrication defects of nanoscale features. Here, we introduce an efficient method to suppress all artifacts by fine-tuning the spatial coherence of illumination. Our method is implemented with a degenerate cavity laser, which allows a precise and continuous tuning of the spatial coherence over a wide range, with little variation in the emission spectrum and total power. We find the optimal degree of spatial coherence to suppress the coherent artifacts of a meta-hologram while maintaining the image sharpness. This work paves the way to compact and dynamical holographic displays free of coherent defects.

Simplified coupling power model for fibers fusion

2009 ◽  
Vol 17 (3) ◽  
Author(s):  
J. Saktioto ◽  
J. Ali ◽  
M. Fadhali
Keyword(s):  
Refractive Index ◽  
Propagation Constant ◽  
Tunable Filter ◽  
Experimental Result ◽  
Total Power ◽  
Optical Parameters ◽  
Coupling Region ◽  
Ratio Distribution ◽  
Hydrogen Flow ◽  
Wide Range

AbstractFiber coupler fabrication used for an optical waveguide requires lossless power for an optimal application. The previous research coupled fibers were successfully fabricated by injecting hydrogen flow at 1 bar and fused slightly by unstable torch flame in the range of 800–1350°C. Optical parameters may vary significantly over wide range physical properties. Coupling coefficient and refractive index are estimated from the experimental result of the coupling ratio distribution from 1% to 75%. The change of geometrical fiber affects the normalized frequency V even for single mode fibers. V is derived and some parametric variations are performed on the left and right hand side of the coupling region. A partial power is modelled and derived using V, normalized lateral phase constant u, and normalized lateral attenuation constant, w through the second kind of modified Bessel function of the l order, which obeys the normal mode and normalized propagation constant b. Total power is maintained constant in order to comply with the energy conservation law. The power is integrated through V, u, and w over the pulling length of 7500 µm for 1-D. The core radius of a fiber significantly affects V and power partially at coupling region rather than wavelength and refractive index of core and cladding. This model has power phenomena in transmission and reflection for an optical switch and tunable filter.

scholarly journals Multi-Mode Wave Energy Converter Design Optimisation Using an Improved Moth Flame Optimisation Algorithm

Energies ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3737
Author(s):  
Mehdi Neshat ◽  
Nataliia Sergiienko ◽  
Seyedali Mirjalili ◽  
Meysam Majidi Nezhad ◽  
Giuseppe Piras ◽  
...  
Keyword(s):  
Wave Energy ◽  
Wave Energy Converter ◽  
Total Power ◽  
Energy Converter ◽  
Wave Regime ◽  
Optimisation Algorithm ◽  
Wide Range ◽  
Evolutionary Optimisation ◽  
Optimisation Methods ◽  
Optimisation Algorithms

Ocean renewable wave power is one of the more encouraging inexhaustible energy sources, with the potential to be exploited for nearly 337 GW worldwide. However, compared with other sources of renewables, wave energy technologies have not been fully developed, and the produced energy price is not as competitive as that of wind or solar renewable technologies. In order to commercialise ocean wave technologies, a wide range of optimisation methodologies have been proposed in the last decade. However, evaluations and comparisons of the performance of state-of-the-art bio-inspired optimisation algorithms have not been contemplated for wave energy converters’ optimisation. In this work, we conduct a comprehensive investigation, evaluation and comparison of the optimisation of the geometry, tether angles and power take-off (PTO) settings of a wave energy converter (WEC) using bio-inspired swarm-evolutionary optimisation algorithms based on a sample wave regime at a site in the Mediterranean Sea, in the west of Sicily, Italy. An improved version of a recent optimisation algorithm, called the Moth–Flame Optimiser (MFO), is also proposed for this application area. The results demonstrated that the proposed MFO can outperform other optimisation methods in maximising the total power harnessed from a WEC.

scholarly journals A Low Energy Clock Network with a Huge Number of Local Synchronized Oscillators

2021 ◽  
Author(s):  
Gunnar Carlstedt ◽  
Mats Rimborg
Keyword(s):  
Clock Cycle ◽  
Internal Clock ◽  
Clock Frequency ◽  
Clock Skew ◽  
Huge Number ◽  
Local Oscillators ◽  
Clock System ◽  
Clock Distribution Network ◽  
Free Running ◽  
Central Clock

<div>A clock system for a huge grid of small clock regions is presented. There is an oscillator in each clock region, which drives the local clock of a processing element (PE). The oscillators are kept synchronized by exploiting the phase of their neighbors. In an infinite mesh, the clock skew would be zero, but in a network of limited size there will be fringe effects. In a mesh with 25×25 oscillators, the maximum skew between neighboring regions is within 3.3 ps. By slightly adjusting the free running frequency of the oscillators, this skew can be reduced to 1.2 ps. The mesh may contain millions of clock regions.</div><div> Because there is no central clock, both power consumption and clock frequency can be improved compared to a conventional clock distribution network. A PE of 150×150 µm² running at 6.7 GHz with 93 master-slave flip-flops is used as an example. The PE-internal clock skew is less than 2.3 ps, and the energy consumption of the clock system 807 µW per PE. It corresponds to an effective gate and wire capacitance of 509 aF, or 7.3 gate capacitances.</div><div> Power noise is reduced by scheduling the local oscillators gradually along one of the grid’s axes. In this way, surge currents, which generally have their peaks at the clock edges, are distributed evenly over a full clock cycle.</div>

A wide-range delay-locked loop with a fixed latency of one clock cycle

2002 ◽  
Vol 37 (8) ◽  
pp. 1021-1027 ◽  
Author(s):  
Hsiang-Hui Chang ◽  
Jyh-Woei Lin ◽  
Ching-Yuan Yang ◽  
Shen-Iuan Liu
Keyword(s):  
Clock Cycle ◽  
Delay Locked Loop ◽  
Wide Range
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