scholarly journals A Novel Ultrasonic TOF Ranging System Using AlN Based PMUTs

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 284
Author(s):  
Yihsiang Chiu ◽  
Chen Wang ◽  
Dan Gong ◽  
Nan Li ◽  
Shenglin Ma ◽  
...  
Keyword(s):  
Clock Cycle ◽  
High Accuracy ◽  
Ultrasonic Waves ◽  
Oxide Semiconductor ◽  
Average Error ◽  
Cmos Process ◽  
Clock Frequency ◽  
Time Frequency ◽  
Range Finding ◽  
Wide Range

This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.

Design and Implementation of a High Accuracy Interpolation Encoder IC for Magnetic Sensor

2019 ◽  
Author(s):  
Wen-Yu Chen ◽  
Yi-Feng Zhang ◽  
Paul C.-P. Chao ◽  
Eka Fitrah Pribadi
Keyword(s):  
Measurement System ◽  
Noise Immunity ◽  
Supply Voltage ◽  
High Accuracy ◽  
Cmos Process ◽  
Specific Method ◽  
Clock Frequency ◽  
Design And Implementation ◽  
Equal Distance ◽  
Interpolation Technique

Abstract The magnetic encoder (ME) always employs sensor passing through periodic and equal distance grating and then generates periodic quadrature scaling signals for displacement measurement. The phase is relative to the movement. To improve encoder accuracy or resolution, electronic interpolation technique had been developed to subdivide the phase of quadrature scaling signals. According to the trends, this paper proposed a specific method with excellent noise immunity characteristic and a complete calibration process to improve the accuracy of the system. The designed circuit is taped-out using TSMC 0.18-μm CMOS process, where the active area is 1643 μm × 1676 μm. The chip has the specification of 3.3 V supply voltage, 20 MHz clock frequency, and 0.0859 mW power consumption. The accuracy of the measurement system is 1.065um.

scholarly journals Predicting atmospheric optical properties for radiative transfer computations using neural networks

2020 ◽  
Author(s):  
Menno Veerman ◽  
Robert Pincus ◽  
Caspar van Leeuwen ◽  
Damian Podareanu ◽  
Robin Stoffer ◽  
...  
Keyword(s):  
Neural Networks ◽  
Optical Properties ◽  
Radiative Transfer ◽  
Grid Cell ◽  
High Accuracy ◽  
Average Error ◽  
Multilayer Perceptrons ◽  
Shallow Convection ◽  
Wide Range ◽  
The Neural Networks

<p>A fast and accurate treatment of radiation in meteorological models is essential for high quality simulations of the atmosphere. Despite our good understanding of the processes governing the transfer of radiation, full radiative transfer solvers are computationally extremely expensive. In this study, we use machine learning to accelerate the optical properties calculations of the Rapid Radiative Transfer Models for General circulation model applications - Parallel (RRTMGP). These optical properties control the absorption, scattering and emission of radiation within each grid cell. We train multiple neural networks that get as input the pressure, temperature and concentrations of water vapour and ozone of each grid cell and together predict all 224 or 256 quadrature points of each optical property. All networks are multilayer perceptrons and we test various network sizes to assess the trade-off between the accuracy of a neural network and its computational costs. We train two different sets of neural networks. The first set (generic) is trained for a wide range of atmospheric conditions, based on the profiles chosen by the Radiative Forcing Model Intercomparison Project (RFMIP). The second set (case-specific) is trained only for the range in temperature, pressure and moisture found in one large-eddy simulation based on a case with shallow convection over a vegetated surface. This case-specific set is used to explore the possible performance gains of case-specific tuning.</p><p>Most neural networks are able to predict the optical properties with high accuracy. Using a network with 2 hidden layers of 64 neurons, predicted optical depths in the longwave spectrum are highly accurate (R<sup>2 </sup>> 0.99). Similar accuracies are achieved for the other optical properties. Subsequently, we take a set of 100 atmospheric profiles and calculate profiles of longwave and shortwave radiative fluxes based on the optical properties predicted by the neural networks. Compared to fluxes based on the optical properties computed by RRTMGP, the downwelling longwave fluxes have errors within 0.5 W m<sup>-2</sup> (<1%) and an average error of -0.011 W m<sup>-2</sup> at the surface. The downwelling shortwave fluxes have an average error of -0.0013 W m<sup>-2</sup> at the surface. Using Intel’s Math Kernel Library’s (MKL) BLAS routines to accelerate matrix multiplications, our implementation of the neural networks in RRTMGP is about 4 times faster than the original optical properties calculations. It can thus be concluded that neural networks are able to emulate the calculation of optical properties with high accuracy and computational speed.</p>

scholarly journals A Highly Accurate, Polynomial-Based Digital Temperature Compensation for Piezoresistive Pressure Sensor in 180 nm CMOS Technology

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5256
Author(s):  
Imran Ali ◽  
Muhammad Asif ◽  
Khuram Shehzad ◽  
Muhammad Riaz Ur Rehman ◽  
Dong Gyu Kim ◽  
...  
Keyword(s):  
Pressure Sensor ◽  
Temperature Compensation ◽  
Absolute Temperature ◽  
Cmos Process ◽  
Measured Temperature ◽  
Signal Conditioning ◽  
Clock Frequency ◽  
Linear Temperature ◽  
Piezoresistive Pressure Sensor ◽  
Wide Range

Recently, piezoresistive-type (PRT) pressure sensors have been gaining attention in variety of applications due to their simplicity, low cost, miniature size and ruggedness. The electrical behavior of a pressure sensor is highly dependent on the temperature gradient which seriously degrades its reliability and reduces measurement accuracy. In this paper, polynomial-based adaptive digital temperature compensation is presented for automotive piezoresistive pressure sensor applications. The non-linear temperature dependency of a pressure sensor is accurately compensated for by incorporating opposite characteristics of the pressure sensor as a function of temperature. The compensation polynomial is fully implemented in a digital system and a scaling technique is introduced to enhance its accuracy. The resource sharing technique is adopted for minimizing controller area and power consumption. The negative temperature coefficient (NTC) instead of proportional to absolute temperature (PTAT) or complementary to absolute temperature (CTAT) is used as the temperature-sensing element since it offers the best temperature characteristics for grade 0 ambient temperature operating range according to the automotive electronics council (AEC) test qualification ACE-Q100. The shared structure approach uses an existing analog signal conditioning path, composed of a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC). For improving the accuracy over wide range of temperature, a high-resolution sigma-delta ADC is integrated. The measured temperature compensation accuracy is within ±0.068% with full scale when temperature varies from −40 °C to 150 °C according to ACE-Q100. It takes 37 µs to compute the temperature compensation with a clock frequency of 10 MHz. The proposed technique is integrated in an automotive pressure sensor signal conditioning chip using a 180 nm complementary metal–oxide–semiconductor (CMOS) process.

scholarly journals Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 21
Author(s):  
Mohamed R. Elmezayen ◽  
Wei Hu ◽  
Amr M. Maghraby ◽  
Islam T. Abougindia ◽  
Suat U. Ay
Keyword(s):  
Process Variations ◽  
Schmitt Trigger ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Original Design ◽  
Accurate Analysis ◽  
Single Input Single Output ◽  
Analysis And Design ◽  
Wide Range ◽  
Single Input

Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used complementary metal-oxide-semiconductor (CMOS) SISO ST circuits. The hysteresis characteristics of these ST circuits were derived for hand calculations and compared to original design equations and simulation results. Simulations were carried out in a well-established, 0.35 μm/3.3 V, analog/mixed-signal CMOS process. Additionally, simulations were performed using a wide range of supplies and process variations, but only 3.3 V supply results are presented. Most of the new design equations provide better accuracy and insights, as broad assumptions of original derivations were avoided.

scholarly journals Hardware Optimized and Error Reduced Approximate Adder

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1212 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas L. Maskell
Keyword(s):  
Integrated Circuit ◽  
Critical Path ◽  
Oxide Semiconductor ◽  
Average Error ◽  
Cmos Process ◽  
Path Delay ◽  
Clock Period ◽  
Design Metrics ◽  
Critical Path Delay ◽  
Reduction In Area

This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)- and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2018.3, targeting an Artix-7 FPGA. The ASIC-based realizations are based on a 32/28nm complementary metal oxide semiconductor (CMOS) process. Based on FPGA implementations, we note the following: (i) For 32-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 22% fewer look-up tables (LUTs) and 18.6% fewer registers while reducing the minimum clock period by 7.1% and reducing the power-delay product (PDP) by 14.7%, compared to the native accurate FPGA adder, and (ii) for 64-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 11% fewer LUTs and 9.3% fewer registers while reducing the minimum clock period by 8.3% and reducing the PDP by 9.3%, compared to the native accurate FPGA adder. Based on ASIC-style implementations, HOERAA is found to achieve the following reductions in design metrics compared to an optimum accurate carry-lookahead adder: (i) A 15.7% reduction in critical path delay, a 21.4% reduction in area, and a 35% reduction in PDP for 32-bit addition involving a 8-bit least significant inaccurate sub-adder, and (ii) a 15.3% reduction in critical path delay, a 10.7% reduction in area, and a 20% reduction in PDP for 64-bit addition involving a 8-bit least significant inaccurate sub-adder. Moreover, comparisons with other approximate adders show that HOERAA has a significantly reduced average error, mean average error, and root mean square error, while reporting near optimum design metrics.

scholarly journals High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Ting-Li Chu ◽  
Sin-Hong Yu ◽  
Chorng-Sii Hwang
Keyword(s):  
Closed Loop ◽  
Clock Cycle ◽  
High Accuracy ◽  
Fine Tuning ◽  
Chip Area ◽  
Delay Locked Loop ◽  
Wide Range ◽  
Instantaneous Switching ◽  
Loop Scheme ◽  
Reference Clock

In this paper, a high-accuracy programmable timing generator with wide-range tuning capability is proposed. With the aid of dual delay-locked loop (DLL), both of the coarse- and fine-tuning mechanisms are operated in precise closed-loop scheme to lessen the effects of the ambient variations. The timing generator can provide sub-gate resolution and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.18 μm 1P6M technology. The test chip area occupies 1.9 mm2. The reference clock cycle can be divided into 128 bins by interpolation to obtain 14 ps resolution with the clock rate at 550 MHz. The INL and DNL are within −0.21~+0.78 and −0.27~+0.43 LSB, respectively.

A 0.0052 mm2 COMPACT DIGITAL PLL IN 65 nm CMOS

2012 ◽  
Vol 21 (08) ◽  
pp. 1240026 ◽  
Author(s):  
ZHIHONG LUO ◽  
YEUNG ON AU ◽  
BENJAMIN LAU ◽  
HENRY LAW
Keyword(s):  
Clock Cycle ◽  
Cell Number ◽  
Ring Oscillator ◽  
Total Power ◽  
Nand Gate ◽  
Clock Frequency ◽  
Clock Jitter ◽  
Delay Cell ◽  
Wide Range ◽  
Reference Clock

A novel structure of digital phase locked loop (PLL) is presented in this paper. It uses digitally controlled oscillator (DCO) to generate the clock. At the beginning of each reference clock cycle, the DCO is fully reset and restarts to oscillate to prevent the long term jitter accumulation and increase the loop stability. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and in cycle load adjust to digitally control the DCO output clock frequency, in order to get wider frequency range and smaller jitter. This digital PLL uses NAND gate as the basic delay cell of ring oscillator, which can completely reset DCO in a very short time. It uses binary search to achieve fast lock and uses shift chain to get better input clock jitter tolerance. This digital PLL has been silicon validated in GLOBALFOUNDRIES 65 nm Generic process. Its chip area is only 0.0052 mm2. In typical condition, DCO's frequency has a wide range between 550 MHz and 2.45 GHz. Its total power is around 1.4 mW when DCO's frequency is 1.8 GHz. This PLL can be locked very fast in 25 divided reference clock cycles, and its output clock jitter is around 18 ps.

Design of Clock and Ramp Generator Circuit Framework with 0.9V Low Operational Voltage

2013 ◽  
Vol 284-287 ◽  
pp. 2502-2508
Author(s):  
Rong Jong Wai ◽  
Jun Jie Liaw
Keyword(s):  
Threshold Voltage ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Clean Energy ◽  
Oxide Semiconductor ◽  
Operational Amplifiers ◽  
Cmos Process ◽  
Clock Frequency ◽  
Ramp Generator ◽  
Generator Circuit

In this study, a new clock and ramp generator circuit framework with a 0.9V low operational voltage is designed for the voltage-mode/current-mode-controlled power management integrated chip of a DC-DC converter. In conventional clock and ramp generator circuit with operational amplifiers, its operational voltage is limited to be over 1.5V because of the problem of a higher threshold voltage in the metal-oxide-semiconductor field-effect transistor (MOSFET). As a result, it can not work well for a pulse-width-modulation DC-DC converter when a below 1V low-voltage single-cell clean-energy power source is applied. This newly-design clock and ramp generator circuit framework without operational amplifiers is investigated to cope with the limitation of the threshold voltage in the MOSFET. Therefore, the corresponding chip size and power consumption can be reduced. Moreover, this circuit still has the functions of adjustable clock frequency and ramp slope. In addition, numerical simulations by the HSPICE software and experimental results by a real chip fabricated in the TSMC 1P6M 0.18µm CMOS process are given to verify the effectiveness of the proposed circuit to produce the clock and ramp waveforms.

scholarly journals High Accuracy Open-Type Current Sensor with a Differential Planar Hall Resistive Sensor

Sensors ◽  
2018 ◽  
Vol 18 (7) ◽  
pp. 2231 ◽  
Author(s):  
Sungho Lee ◽  
Sungmin Hong ◽  
Wonki Park ◽  
Wonhyo Kim ◽  
Jaehoon Lee ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Integrated Circuit ◽  
High Accuracy ◽  
Magnetic Sensors ◽  
Oxide Semiconductor ◽  
Current Sensor ◽  
Cmos Process ◽  
Open Type ◽  
Differential Structure ◽  
A Current

In this paper, we propose a high accuracy open-type current sensor with a differential Planar Hall Resistive (PHR) sensor. Conventional open-type current sensors with magnetic sensors are usually vulnerable to interference from an external magnetic field. To reduce the effect of an unintended magnetic field, the proposed design uses a differential structure with PHR. The differential structure provides robust performance to unwanted magnetic flux and increased magnetic sensitivity. In addition, instead of conventional Hall sensors with a magnetic concentrator, a newly developed PHR with high sensitivity is employed to sense horizontal magnetic fields. The PHR sensor and read-out integrated circuit (IC) are integrated through a post-Complementary metal-oxide-semiconductor (CMOS) process using multi-chip packaging. The current sensor is designed to measure a 1 A current level. The measured performance of the designed current sensor has a 16 kHz bandwidth and a current nonlinearity of under ±0.5%.

scholarly journals Lossless Decompression Accelerator for Embedded Processor with GUI

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 145
Author(s):  
Gwan Beom Hwang ◽  
Kwon Neung Cho ◽  
Chang Yeop Han ◽  
Hyun Woo Oh ◽  
Young Hyun Yoon ◽  
...  
Keyword(s):  
Embedded System ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Clock Frequency ◽  
Embedded Processor ◽  
Mobile Industry ◽  
Field Programmable ◽  
The Embedded System

The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (SoC) for the embedded system. In this paper, we propose a lossless decompression accelerator for an embedded processor, which supports LZ77 decompression and static Huffman decoding for an inflate algorithm. The accelerator is implemented on a field programmable gate array (FPGA) to verify the functional suitability and fabricated in a Samsung 65 nm complementary metal oxide semiconductor (CMOS) process. The performance of the accelerator is evaluated by the Canterbury corpus benchmark and achieved throughput up to 20.7 MB/s at 50 MHz system clock frequency.

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