scholarly journals Design and analysis of different full adder cells using new technologies

2020 ◽  
Vol 9 (2) ◽  
pp. 116
Author(s):  
Nandhaiahgari Dinesh Kumar ◽  
Rajendra Prasad Somineni ◽  
CH Raja Kumari
Keyword(s):  
New Technologies ◽  
Supply Voltage ◽  
Full Adder ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Effect Transistor ◽  
Scaling Down ◽  
Process Transfer

<span>CMOS transistors are most widely used for the design of computerized circuits, when scaling down the nanometer technology these devices faces the short channel effects and causes I-V characteristics to depart from the traditional MOSFETs, So the researchers have developed the other transistors technologies like CNTFET and GNRFET. Carbon nanotube field effect transistor is one of the optimistic technologies and it is a three terminal transistor similar to MOSFET. The semiconducting channel between the two terminals called source and drain comprises of the nano tube which is made of carbon. Graphene nano ribbon filed effect transistor is the most optimistic technology here the semiconducting channel is made of graphene. When contrasted with barrel shaped CNTFETs, GNRFETs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage related and alignment problems as faced in CNTFET devices. This paper presents different 1-bit Full Adder Cells (FACs) like TG MUX-based FAC (TGM), MN MUX-based FAC (MNM), proposed TG Modified MUX-based FAC (TGMM) and another proposed MN Modified MUX-based FAC (MNMM) are designed using different technologies like CNTFET and GNRFET at 16nm technology with supply voltage of 0.85v and simulation is done by using Synopsys HSPICE Tool and the proposed designs are best when compared to the TGM and MNM FACs in terms of Static and Dynamic powers Dissipations and Delay.</span>

Synthesis of Low-Voltage Logic Gates on Surrounding Gate SOI CMOS Nanotransistors

2021 ◽  
Vol 23 (2) ◽  
pp. 75-82
Author(s):  
Masalsky N.V. ◽  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Logic Gates ◽  
Active Power ◽  
Short Channel Effects ◽  
Short Channel ◽  
Switching Delay ◽  
Surrounding Gate ◽  
Channel Effects ◽  
Soi Cmos

We discuss the issues of synthesis of low-voltage logic gates on cylindrical surrounding gate SOI CMOS nanotransistors in the supply voltage range up to 0.8 V. In this transistor architecture, it becomes possible to more effectively control the charge in its working area, primarily due to its design parameters. It is also characterized by effective suppression of short-channel effects and a low capacitance value. This leads to a decrease in the level of power dissipation in combination with a reduction in the occupied area. TCAD models of n- and p-types nanotransistors have been developed. The anomalous behavior of the dependence of the threshold voltage on the diameter of the working area is revealed, which is associated with the peculiarities of the manifestation of short-channel effects due to the capacitive interaction of the gate-channel regions and drain-source transitions at small gate lengths. They were used to select prototypes of transistors with optimal parameters for the synthesis of complex logic gates with low supply voltage. Using the mathematical core of the HSPICE program, the dynamic characteristics of the developed physical models of the inverter, the inverter chain, and the XOR2 are numerically investigated. At control voltages of 0.8 V and a frequency of 50 GHz, the inverter model predicts a maximum switching delay of 3.3 ps, a limit level of active power of 1.1 mkW, static 0.3 pW, the XOR2 predicts a maximum switching delay of 8.6 ps, a limit level of active power of 4.9 mkW, static 1.5 pW. The minimum of the product "delay * power" of the adder is at a supply voltage of 0.72 V. Its position does not depend on the set of input signals. At the same time, the maximum switching delay is 10.8 ps, the maximum active power level is 3.9 mkW. The totality of the obtained characteristics allows us to consider the analyzed transistor architecture for creating low-power electronic devices.

Etching Effects of Nanotechnology Fabrication on CMOS Transistor Gate Wafer Manufacturing Process Integration

2010 ◽  
Vol 154-155 ◽  
pp. 938-941
Author(s):  
Chun Jen Weng
Keyword(s):  
Process Integration ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Fabrication Technology ◽  
Short Channel ◽  
Channel Effects ◽  
Cmos Transistor ◽  
Scaling Down ◽  
Wafer Manufacturing

As wafer nanotechnology gate is scaling down, the fabrication technology of gate spacer for transistor becomes more critical in manufacturing processes. Because wafer fabrication technologies, sidewall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present study is to overcome the fabrication processes limitations and proposed modified feasible etching processes integration on the formation processing for complementary metal oxide semiconductor nanofabrication process of gate spacer technology and electrical characteristics.

scholarly journals A Unified Channel Charges Expression for Analytic MOSFET Modeling

2012 ◽  
Vol 2012 ◽  
pp. 1-12 ◽  
Author(s):  
Hugues Murray ◽  
Patrick Martin
Keyword(s):  
Drain Current ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Efficient Tool ◽  
Equation Resolution ◽  
Weak Inversion ◽  
Analytical Functions ◽  
Channel Effects ◽  
Effect Transistor

Based on a 1D Poissons equation resolution, we present an analytic model of inversion charges allowing calculation of the drain current and transconductance in the Metal Oxide Semiconductor Field Effect Transistor. The drain current and transconductance are described by analytical functions including mobility corrections and short channel effects (CLM, DIBL). The comparison with the Pao-Sah integral shows excellent accuracy of the model in all inversion modes from strong to weak inversion in submicronics MOSFET. All calculations are encoded with a simple C program and give instantaneous results that provide an efficient tool for microelectronics users.

scholarly journals Design and software characterization of finFET based full adders

2019 ◽  
Vol 8 (1) ◽  
pp. 51
Author(s):  
Raju Hajare ◽  
C. Lakshminarayana
Keyword(s):  
Field Effect Transistors ◽  
Full Adder ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Switching Speed ◽  
Chip Area ◽  
Channel Effects ◽  
Technology Nodes

Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various  technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.

scholarly journals A Literature Survey on Tunnel Field Effect Transistors

2021 ◽  
Author(s):  
Soumya Sen ◽  
Ashish Raman ◽  
Mamta Khosla
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Tunneling Current ◽  
Short Channel Effects ◽  
Short Channel ◽  
Vast Number ◽  
Different Types ◽  
Channel Effects ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

TFET or Tunnel Field Effect Transistor in recent times has been the center of attraction of vast number of researcher’s despite of having minute subthreshold slope and excessive Ion/Ioff ratio. It is known that TFETs are much more immune to short-channel effects and fluctuations of random dopants in comparison to their MOSFET counterparts. TFETs are actually gated p-i-n diodes having tunneling current flowing between source and channel bands. In this paper deep rooted literature review has been done scanning each and every aspects of TFET including the variations of performance with different parameters. The paper finally gives a picture on the recent progress of TFET in different aspects such as from subthreshold swing to a significantly lower leakage current and high on current .For the simulation curves Nanohub.org was used as a tool. Lastly different types of TFET in respect of doping to symmetry and also gates are compared.

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