scholarly journals Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing

2018 ◽  
Vol 51 (7-8) ◽  
pp. 235-242 ◽  
Author(s):  
Arulmurugan Azhaganantham ◽  
Murugesan Govindasamy
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Power Distribution ◽  
Large Scale ◽  
Heat Dissipation ◽  
Peak Temperature ◽  
Heating Event ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

High temperature occurs in testing of complex System-on-Chip designs and it may become a critical concern to be carefully taken into account with continual development in Very Large Scale Integration technology. Peak temperature significantly affects the reliability and the performance of the chip. So it is essential to minimize the peak temperature of the chip. Heat generation by power consumption and heat dissipation to the surrounding blocks are the two prominent factors for the peak temperature. Power consumption can be minimized by a careful mapping of don’t cares in precomputed test set. However, it does not provide the solution to peak temperature minimization because the non-uniformity in spatial power distribution may create localized heating event called “hotspot.” The peak temperature on the hotspot is minimized by Genetic Algorithm–based don’t care filling technique that reduces the non-uniformity in spatial power distribution within the circuit under test while maintaining the overall power consumption at a lower level. Experimental results on ISCAS89 benchmark circuits demonstrate that 6%–28% peak temperature reduction can be achieved.

scholarly journals Investigation of the Impact of Large-Scale Integration of Electric Vehicles for a Swedish Distribution Network

Energies ◽  
2019 ◽  
Vol 12 (24) ◽  
pp. 4717 ◽  
Author(s):  
Sylvester Johansson ◽  
Jonas Persson ◽  
Stavros Lazarou ◽  
Andreas Theocharis
Keyword(s):  
Electric Vehicles ◽  
Power Distribution ◽  
Large Scale ◽  
Electrical Power ◽  
Distribution Network ◽  
Transport Sector ◽  
Smart Charging ◽  
Large Scale Integration ◽  
Scale Integration ◽  
The Impact

Social considerations for a sustainable future lead to market demands for electromobility. Hence, electrical power distribution operators are concerned about the real ongoing problem of the electrification of the transport sector. In this regard, the paper aims to investigate the large-scale integration of electric vehicles in a Swedish distribution network. To this end, the integration pattern is taken into consideration as appears in the literature for other countries and applies to the Swedish culture. Moreover, different charging power levels including smart charging techniques are examined for several percentages of electric vehicles penetration. Industrial simulation tools proven for their accuracy are used for the study. The results indicate that the grid can manage about 50% electric vehicles penetration at its current capacity. This percentage decreases when higher charging power levels apply, while the transformers appear overloaded in many cases. The investigation of alternatives to increase the grid’s capabilities reveal that smart techniques are comparable to the conventional re-dimension of the grid. At present, the increased integration of electric vehicles is manageable by implementing a combination of smart gird and upgrade investments in comparison to technically expensive alternatives based on grid digitalization and algorithms that need to be further confirmed for their reliability for power sharing and energy management.

Interface Characterization of Metallized CVD Diamond

1998 ◽  
Vol 4 (S2) ◽  
pp. 778-779
Author(s):  
E. S. K. Menon ◽  
M. Saunders ◽  
I. Dutta
Keyword(s):  
Large Scale ◽  
Heat Dissipation ◽  
Heat Sinks ◽  
Active Devices ◽  
Diamond Substrate ◽  
Large Scale Integration ◽  
Innovative Materials ◽  
Scale Integration ◽  
Electronics Packages

Progress towards the large scale integration of active devices within electronics packages has imposed stringent heat dissipation requirements necessitating the development of innovative materials solutions. One possibility being considered is the use of chemically vapor deposited diamond (CVDD) thin films as heat sinks. However, there are technological challenges which must be overcome before these materials become commercially viable. For example, the CVDD substrate must be metallized to provide interconnections between the various devices in the package. Conventional metallizations, such as Au, Cu or Al, display poor adhesion to the diamond causing problems associated with the reliability and stability of metallized diamond packages. A novel solution has been proposed involving the consecutive deposition of a thin layer of Cr and an electrically insulating layer of alumina on the diamond substrate such that the thermal conductivity of the treated substrate is not degraded significantly.

The Optimized Charge-Discharge Strategy of EVs Considering the Fluctuation of Wind Power

2014 ◽  
Vol 521 ◽  
pp. 151-156
Author(s):  
Sheng Wei Tang ◽  
Yi Tan ◽  
Juan Liu ◽  
Jian Wei Sun
Keyword(s):  
Genetic Algorithm ◽  
Wind Power ◽  
Large Scale ◽  
Control Model ◽  
Power Fluctuation ◽  
Discharge Characteristics ◽  
The Monte Carlo Method ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Charge Discharge

The fluctuation is an important factor that limits large-scale integration of wind power into power grid. In order to improve penetration level of wind power, the EVs based on V2G are considered to participate in regulating wind power while considering charge-discharge characteristics of EV battery. Thus, in this paper, an optimized EV charge-discharge control model is proposed to reduce output fluctuation of wind power. The Monte-Carlo method is used to simulate the stochastic wind speed based on Weibull probability density function. Finally, Genetic Algorithm (GA) is adopted to solve the problem. Results indicate that the EVs based on V2G can reduce the wind power fluctuation level to some extent, absorbing the wind power surplus and compensating the of wind power shortage.

Directed Assembly of Metal Oxide Nanobelts With Microsystems Into Integrated Nanosensors

2004 ◽  
Author(s):  
Choongho Yu ◽  
Qing Hao ◽  
Li Shi ◽  
Dae-Jin Kang ◽  
Xiangyang Kong ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Gas Sensors ◽  
Large Scale ◽  
Tin Dioxide ◽  
Electrical Conductance ◽  
Directed Assembly ◽  
Large Scale Integration ◽  
Sno2 Nanobelts ◽  
Scale Integration

Single-crystalline tin dioxide (SnO2) nanobelts have been assembled with microfabricated suspended heaters as low-power, sensitive gas sensors. With less than 4 mW power consumption of the micro-heater, the nanobelt can be heated up to 500°C. The electrical conductance of the heated nanobelt was found to be highly stable and sensitive to toxic and inflammable gas species including dimethyl methyl phosphonate (DMMP), nitrogen dioxide (NO2), and ethanol. The experiment is a step towards the large scale integration of nanomaterials with microsystems, and such integration via a directed assembly approach can potentially enable the fabrication of low-power, sensitive, and selective integrated nanosensor systems.

Self-Adaptive SoCs for Dependability

2014 ◽  
pp. 1-21
Author(s):  
Liang Guang ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
Large Scale ◽  
Future Research ◽  
Great Promise ◽  
Primary Concern ◽  
Technology Scaling ◽  
Computing Paradigm ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Self Adaptive

Dependability is a primary concern for emerging billion-transistor SoCs (Systems-on-Chip), especially when the constant technology scaling introduces an increasing rate of faults and errors. Considering the time-dependent device degradation (e.g. caused by aging and run-time voltage and temperature variations), self-adaptive circuits and architectures to improve dependability is promising and very likely inevitable. This chapter extensively surveys existing works on monitoring, decision-making, and reconfiguration addressing different dependability threats to Very Large Scale Integration (VLSI) chips. Centralized, distributed, and hierarchical fault management, utilizing various redundancy schemes and exploiting logical or physical reconfiguration methods, are all examined. As future research directions, the challenge of integrating different error management schemes to account for multifold threats and the great promise of error resilient computing are identified. This chapter provides, for chip designers, much needed insights on applying a self-adaptive computing paradigm to approach dependability on error-prone, cost-sensitive SoCs.

Porous low dielectric constant materials for microelectronics

2005 ◽  
Vol 364 (1838) ◽  
pp. 201-215 ◽  
Author(s):  
Mikhail R Baklanov ◽  
Karen Maex
Keyword(s):  
Dielectric Constant ◽  
High Speed ◽  
Large Scale ◽  
Low Dielectric Constant ◽  
Low Dielectric ◽  
Large Scale Integration ◽  
The Subject ◽  
On Chip ◽  
Scale Integration ◽  
Selection Of

Materials with a low dielectric constant are required as interlayer dielectrics for the on-chip interconnection of ultra-large-scale integration devices to provide high speed, low dynamic power dissipation and low cross-talk noise. The selection of chemical compounds with low polarizability and the introduction of porosity result in a reduced dielectric constant. Integration of such materials into microelectronic circuits, however, poses a number of challenges, as the materials must meet strict requirements in terms of properties and reliability. These issues are the subject of the present paper.

Overview Of Process Integration Issues For Low K Dielectrics

1998 ◽  
Vol 511 ◽  
Author(s):  
R. H. Havemann ◽  
M. K. Jain ◽  
R. S. List ◽  
A. R. Ralston ◽  
W-Y. Shih ◽  
...  
Keyword(s):  
Large Scale ◽  
Process Integration ◽  
Functional Integration ◽  
Dielectric Materials ◽  
Limiting Factor ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Rc Delay ◽  
Low K

ABSTRACTThe era of silicon Ultra-Large-Scale-Integration (ULSI) has spurred an everincreasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. Both interconnect resistance and capacitance play key roles in overall performance, but modeling simulations have highlighted the importance of reducing parasitic capacitance to manage crosstalk, power dissipation and RC delay. New dielectric materials with lower permittivity (k) are needed to meet this challenge. This paper summarizes the process integration and reliability issues associated with the use of novel low k materials in multilevel interconnects.

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