Complementary Metal Oxide Semiconductor Amplifier Behaviour Considering Different Points of Electromagnetic Interference Injection

2019 ◽  
Vol 15 (4) ◽  
pp. 361-367 ◽  
Author(s):  
Simone Becchetti ◽  
Anna Richelli ◽  
Luigi Colalongo ◽  
Zsolt M. Kovacs-Vajna
Keyword(s):  
Metal Oxide ◽  
Critical Point ◽  
Electromagnetic Interference ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Fair Comparison ◽  
Folded Cascode ◽  
Cmos Amplifier

In this paper the CMOS amplifier behaviour has been further investigated respect to the previous works in the literature. An exhaustive scenario for the EMI pollution has been considered: the injected interferences can indeed directly reach the amplifier pins or can be coupled from the PCB ground. This is a key point for evaluating also the susceptibility from the EMI coupled to the output pin, which is disclosed as a critical point. The investigated topologies are basically derived from the Miller and the Folded Cascode, which are well-known and widely used by the CMOS analog designers; all of them are re-designed in UMC 180 nm CMOS process in order to have a fair comparison.

scholarly journals A Comprehensive Comparison of EMI Immunity in CMOS Amplifier Topologies

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1181 ◽  
Author(s):  
Simone Becchetti ◽  
Anna Richelli ◽  
Luigi Colalongo ◽  
Zsolt Kovacs-Vajna
Keyword(s):  
Electromagnetic Interference ◽  
Printed Circuit Board ◽  
Complementary Metal Oxide Semiconductor ◽  
Circuit Board ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Fair Comparison ◽  
Comprehensive Comparison ◽  
Folded Cascode ◽  
Cmos Amplifier

This paper provides the results of a comprehensive comparison between complementary metal oxide semiconductor (CMOS) amplifiers with low susceptibility to electromagnetic interference (EMI). They represent the state-of-the-art in low EMI susceptibility design. An exhaustive scenario for EMI pollution has been considered: the injected interference can indeed directly reach the amplifier pins or can be coupled from the printed circuit board (PCB) ground. This is also a key point for evaluating the susceptibility from EMI coupled to the output pin. All of the amplifiers are re-designed in a United Microelectronics Corporation (UMC) 180 nm CMOS process in order to have a fair comparison. The topologies investigated and compared are basically derived from the Miller and the folded cascode ones, which are well-known and widely used by CMOS analog designers.

scholarly journals Universal Filter Based on Compact CMOS Structure of VDDDA

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1683
Author(s):  
Winai Jaikla ◽  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Koson Pitaksuttayaprot
Keyword(s):  
Metal Oxide ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Experimental Results ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Voltage Gain ◽  
Universal Filter ◽  
Mos Transistor

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

scholarly journals A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes

Sensors ◽  
2019 ◽  
Vol 19 (19) ◽  
pp. 4149
Author(s):  
Xiang Li ◽  
Rui Li ◽  
Chunge Ju ◽  
Bo Hou ◽  
Qi Wei ◽  
...  
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Output Voltage ◽  
Charge Pump ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Temperature Changes ◽  
Adjustable Range

Micromachined gyroscopes require high voltage (HV) for actuation and detection to improve its precision, but the deviation of the HV caused by temperature fluctuations will degrade the sensor’s performance. In this paper, a high-voltage temperature-insensitive charge pump is proposed. Without adopting BCD (bipolar-CMOS-DMOS) technology, the output voltage can be boosted over the breakdown voltage of n-well/substrate diode using triple-well NMOS (n-type metal-oxide-semiconductor) transistors. By controlling the pumping clock’s amplitude continuously, closed-loop regulation is realized to reduce the output voltage’s sensitivity to temperature changes. Besides, the output level is programmable linearly in a large range by changing the reference voltage. The whole circuit has been fabricated in a 0.18- μ m standard CMOS (complementary metal-oxide-semiconductor) process with a total area of 2.53 mm 2 . Measurements indicate that its output voltage has a linear adjustable range from around 13 V to 16.95 V, and temperature tests show that the maximum variations of the output voltage at − 40 ∼ 80 ∘ C are less than 1.1%.

scholarly journals Magnetic Micro Sensors with Two Magnetic Field Effect Transistors Fabricated Using the Commercial Complementary Metal Oxide Semiconductor Process

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4731
Author(s):  
Wei-Ren Chen ◽  
Yao-Chuan Tsai ◽  
Po-Jen Shih ◽  
Cheng-Chih Hsu ◽  
Ching-Liang Dai
Keyword(s):  
Magnetic Field ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Magnetic Field Effect ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Micro Sensor

The fabrication and characterization of a magnetic micro sensor (MMS) with two magnetic field effect transistors (MAGFETs) based on the commercial complementary metal oxide semiconductor (CMOS) process are investigated. The magnetic micro sensor is a three-axis sensing type. The structure of the magnetic microsensor is composed of an x/y-MAGFET and a z-MAGFET. The x/y-MAGFET is employed to sense the magnetic field (MF) in the x- and y-axis, and the z-MAGFET is used to detect the MF in the z-axis. To increase the sensitivity of the magnetic microsensor, gates are introduced into the two MAGFETs. The sensing current of the MAGFET enhances when a bias voltage is applied to the gates. The finite element method software Sentaurus TCAD was used to analyze the MMS’s performance. Experiments show that the MMS has a sensitivity of 182 mV/T in the x-axis MF and a sensitivity of 180 mV/T in the y-axis MF. The sensitivity of the MMS is 27.8 mV/T in the z-axis MF.

A Novel Maskless Post-CMOS Bulk Micromachining Process

2003 ◽  
Author(s):  
Jing-Hung Chiou ◽  
Ching-Liang Dai ◽  
Jen-Yi Chen ◽  
Michael S.-C. Lu
Keyword(s):  
Metal Oxide ◽  
Silicon Substrate ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Wet Etching ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Deep Cavity ◽  
Deep Cavities ◽  
Tmah Solution

This work describes a new post-CMOS (Complementary Metal Oxide Semiconductor) bulk micromachining process for fabrication of various microstructures. The important feature of the post-CMOS process is the use of wet etching without an addition mask, to form various microstructures and deep cavities in the silicon substrate. The post-CMOS process starts with wet etching to remove sacrificial layers, which are stacked layers of metals and vias, to expose the silicon substrate. Then, KOH or TMAH solution is employed to etch the silicon substrate to form various deep cavities and suspended structures. Many suspended structures, which include beams, bridges and plates, are fabricated using the standard 0.35-μm SPFM (Single Polysilicon Four Metal) CMOS process and the post-CMOS process. Experimental results reveals that a plate with an area of 200×200 μm2, a bridge with a length of 300μm, and various beams with lengths from 100-μm to 400-μm suspended on a deep cavity were fabricated successfully.

Fabrication of microbridges in standard complementary metal oxide semiconductor technology

1989 ◽  
Vol 67 (4) ◽  
pp. 184-189 ◽  
Author(s):  
M. Parameswaran ◽  
Lj. Ristic ◽  
A. C. Dhaded ◽  
H. P. Baltes ◽  
W. Allegretto ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Layout Design ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Digital Cmos ◽  
Sensor Applications

Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of microbridges, bare polysilicon microbridges and sandwiched oxide microbridges, have been manufactured by first implementing a special layout design in an industrial digital CMOS process, followed by a postprocessing etching step.

scholarly journals MPPT Circuit Using Time Exponential Rate Perturbation and Observation for Enhanced Tracking Efficiency for a Wide Resistance Range of Thermoelectric Generator

2021 ◽  
Vol 11 (10) ◽  
pp. 4650
Author(s):  
Jie Miao ◽  
Houpeng Chen ◽  
Yu Lei ◽  
Yi Lv ◽  
Weili Liu ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Thermoelectric Generator ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Maximum Power ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Exponential Rate ◽  
Point Tracking ◽  
High Level

The thermoelectric generator (TEG) stands out among many energy harvesters due to its simple structure, small size, rich thermal energy, and the absence of pollution and noise. However, previous studies have rarely probed into the influence of TEG internal resistances on extracting maximum power from TEGs, and the tracking of efficiency is limited. By analyzing the relationship between the tracking efficiency and the TEG internal resistances, a time exponential rate perturbation and observation (P&O) technology is proposed to achieve maximum power point tracking (MPPT) for a wide resistance range of the TEG. Using the time exponential rate P&O, the MPPT circuit observed the power change by comparing the positive-channel metal-oxide semiconductor (PMOS) on-time and perturbs the power by adjusting the negative-channel metal-oxide semiconductor (NMOS) on-time exponentially. The MPPT circuit was implemented in a 110 nm complementary metal-oxide semiconductor (CMOS) process. The tracking efficiency maintained a high level from 98.9 to 99.5%. The applicable range of the TEG resistance was from 1 to 12 Ω, which reflects an enhancement of at least 2.2 times.

scholarly journals Improving the Performance of the ToGoFET Probe: Advances in Design, Fabrication, and Signal Processing

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1303
Author(s):  
Hoontaek Lee ◽  
Junsoo Kim ◽  
Kumjae Shin ◽  
Wonkyu Moon
Keyword(s):  
Signal Processing ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Complementary Metal Oxide Semiconductor ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Effect Transistor

We report recent improvements of the tip-on-gate of field-effect-transistor (ToGoFET) probe used for capacitive measurement. Probe structure, fabrication, and signal processing were modified. The inbuilt metal-oxide-semiconductor field-effect-transistor (MOSFET) was redesigned to ensure reliable probe operation. Fabrication was based on the standard complementary metal-oxide-semiconductor (CMOS) process, and trench formation and the channel definition were modified. Demodulation of the amplitude-modulated drain current was varied, enhancing the signal-to-noise ratio. The - characteristics of the inbuilt MOSFET reflect the design and fabrication modifications, and measurement of a buried electrode revealed improved ToGoFET imaging performance. The minimum measurable value was enhanced 20-fold.

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