scholarly journals A High Speed and Wide Frequency Division Range Mixed-Signal Pulse Swallow Frequency Divider for Phase-Locked-Loop

2021 ◽  
Author(s):  
Yimeng Zhao ◽  
Haiyang Quan ◽  
Zengrong Liu
Keyword(s):  
High Speed ◽  
Phase Locked Loop ◽  
Frequency Divider ◽  
Signal Pulse ◽  
Frequency Division ◽  
Mixed Signal

scholarly journals A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process

2021 ◽  
Vol 2132 (1) ◽  
pp. 012046
Author(s):  
Muzhen Hao ◽  
Xiaodong Liu ◽  
Zhizhe Liu ◽  
Feng Ji ◽  
Di Sun ◽  
...  
Keyword(s):  
Phase Noise ◽  
High Frequency ◽  
High Speed ◽  
Frequency Divider ◽  
Cmos Process ◽  
Frequency Division ◽  
Frequency Range ◽  
Flip Flop ◽  
Large Bandwidth ◽  
Level 2

Abstract This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

scholarly journals A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2494
Author(s):  
Lu Tang ◽  
Kuidong Chen ◽  
Youming Zhang ◽  
Xusheng Tang ◽  
Changchun Zhang
Keyword(s):  
High Speed ◽  
Frequency Synthesizer ◽  
Phase Locked Loop ◽  
Frequency Divider ◽  
Flip Flop ◽  
Ka Band ◽  
Locking Range ◽  
Type Frequency ◽  
Operation Frequency ◽  
Programmable Frequency Divider

A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low phase noise of less than −136 dBc/Hz at a 1 MHz offset of output signals, an optimum sensitivity of −27 dBm at 15 GHz, and a low power consumption of 9.1 mW.

An IC Mixed-Signal Framework for Design, Optimization, and Verification of High-Speed Links

2020 ◽  
Author(s):  
Gabriel Madrigal-Boza ◽  
Marco Oviedo-Hernandez ◽  
Allan Carmona-Cruz ◽  
Luis A. Chavarria-Zamora ◽  
Daniel Leon-Gamboa ◽  
...  
Keyword(s):  
Design Optimization ◽  
High Speed ◽  
Mixed Signal
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