Subthreshold Swing for Top and Bottom Gate Oxide Thickness of Asymmetric Double Gate MOSFET

2013 ◽  
Author(s):  
Hakkee Jung ◽  
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Subthreshold Swing ◽  
Double Gate ◽  
Gate Oxide Thickness ◽  
Double Gate Mosfet ◽  
Bottom Gate

A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry

2014 ◽  
Vol 61 (8) ◽  
pp. 2732-2737 ◽  
Author(s):  
Neha Sharan ◽  
Santanu Mahapatra
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Double Gate ◽  
Short Channel ◽  
Gate Oxide Thickness ◽  
Double Gate Mosfet

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

2012 ◽  
Vol 59 (4) ◽  
pp. 1002-1007 ◽  
Author(s):  
Srivatsava Jandhyala ◽  
Rutwick Kashyap ◽  
Costin Anghel ◽  
Santanu Mahapatra
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Double Gate ◽  
Charge Model ◽  
Gate Oxide Thickness

scholarly journals Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

2021 ◽  
Vol 11 (1) ◽  
pp. 240
Author(s):  
Hakkee Jung
Keyword(s):  
Dielectric Constant ◽  
Oxide Film ◽  
Gate Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Subthreshold Swing ◽  
Asymmetric Structure ◽  
Double Gate ◽  
High K

In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

scholarly journals Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

2019 ◽  
Vol 9 (1) ◽  
pp. 163
Author(s):  
Hakkee Jung
Keyword(s):  
Threshold Voltage ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Double Gate ◽  
Short Channel ◽  
Double Gate Mosfet ◽  
Channel Effects ◽  
Channel Thickness

Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

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