scholarly journals Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

2021 ◽  
Vol 11 (1) ◽  
pp. 240
Author(s):  
Hakkee Jung
Keyword(s):  
Dielectric Constant ◽  
Oxide Film ◽  
Gate Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Subthreshold Swing ◽  
Asymmetric Structure ◽  
Double Gate ◽  
High K

In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

scholarly journals Subthreshold swing model using scale length for sub-10 nm junction-based double-gate MOSFETs

2020 ◽  
Vol 10 (2) ◽  
pp. 1747
Author(s):  
Hakkee Jung
Keyword(s):  
Analytical Model ◽  
Potential Distribution ◽  
Geometric Mean ◽  
Oxide Thickness ◽  
Channel Length ◽  
Subthreshold Swing ◽  
Double Gate ◽  
Silicon Thickness ◽  
The Relationship ◽  
Scale Length

We propose an analytical model for subthreshold swing using scale length for sub-10 nm double gate (DG) MOSFETs. When the order of the calculation for the series type potential distribution is increased it is possible to obtain accuracy, but there is a problem that the calculation becomes large. Using only the first order calculation of potential distribution, we derive the scale length λ1 and use it to obtain an analytical model of subthreshold swing. The findings show this subthreshold swing model is in concordance with a 2D simulation. The relationship between the channel length and silicon thickness, which can analyze the subthreshold swing using λ1, is derived by the relationship between the scale length and the geometric mean of the silicon and oxide thickness. If the silicon thickness and oxide film thickness satisfy the condition of (Lg-0.215)/6.38 > tsi(=tox), it is found that the result of this model agrees with the results using higher order calculations, within a 4% error range.

scholarly journals Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

2019 ◽  
Vol 9 (1) ◽  
pp. 163
Author(s):  
Hakkee Jung
Keyword(s):  
Threshold Voltage ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Double Gate ◽  
Short Channel ◽  
Double Gate Mosfet ◽  
Channel Effects ◽  
Channel Thickness

Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

scholarly journals Parameter Analysis of CNTFET

2019 ◽  
Vol 8 (2) ◽  
pp. 5355-5359
Keyword(s):  
Dielectric Constant ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Parameter Analysis ◽  
Source Voltage

In this paper, a parameter analysis of CNTFET is presented with different parameters variations such as gate to source voltage vgs, oxide thickness tox, gate oxide dielectric Kox, channel length L, source/drain spacer dielectric constant Kspa ect. All the parameters of CNTFET have been varied in CADENCE Virtuoso environment and verified with the preferred value of stanford VS-CNTFET model

scholarly journals Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET

2021 ◽  
Vol 11 (1) ◽  
pp. 232
Author(s):  
Hakkee Jung
Keyword(s):  
Threshold Voltage ◽  
Gate Voltage ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Length ◽  
Double Gate ◽  
Static Feedback ◽  
Silicon Thickness ◽  
Relationship Of ◽  
Bottom Gate

The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L) × 10-7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is obtained. As a result, we observe the DIBL is proportional to the negative third power of the channel length and the second power of the silicon thickness and linearly proportional to the geometric mean of the top and bottom gate oxide thicknesses, and derive a relation such as DIBL =25.15ηL_g^(-3) t_si^2 √(t_ox1∙t_ox2 ), where η is a static feedback coefficients between 0 and 1. The η is found to be between 0.5 and 1.0 in this model. The DIBL model of this paper has been observed to be in good agreement with the result of other paper, so it can be used in circuit simulation such as SPICE.

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

2021 ◽  
Author(s):  
SHIKHA U S ◽  
Rekha K James ◽  
Jobymol Jacob ◽  
Anju Pradeep
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Negative Capacitance ◽  
Double Gate ◽  
High K ◽  
Gate Control ◽  
Effect Transistor ◽  
Dimensional Simulation ◽  
The Impact ◽  
Low K

Abstract The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

scholarly journals Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric

2008 ◽  
Vol 2008 ◽  
pp. 1-5 ◽  
Author(s):  
A. Bouazra ◽  
S. Abdi-Ben Nasrallah ◽  
M. Said ◽  
A. Poncet
Keyword(s):  
Dielectric Constant ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Gate Leakage ◽  
Mos Devices ◽  
High K ◽  
Carrier Trap ◽  
High Dielectric ◽  
Very High ◽  
Tunnelling Current

With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.

Study of Linearity Performance of Graded Channel Gate Stacks Double Gate MOSFET with Respect to High-K Oxide Thickness

Silicon ◽  
2019 ◽  
Vol 12 (7) ◽  
pp. 1567-1574
Author(s):  
Sanjit Kumar Swain ◽  
Satish Kumar Das ◽  
Sarosij Adak
Keyword(s):  
Oxide Thickness ◽  
Double Gate ◽  
Gate Stacks ◽  
High K ◽  
Double Gate Mosfet ◽  
Channel Gate

Alternate Gate Oxides for Silicon Mosfets Using High-k Dielectrics

1999 ◽  
Vol 567 ◽  
Author(s):  
C. A. Billman ◽  
P. H. Tan ◽  
K. J. Hubbard ◽  
D. G. Schlom
Keyword(s):  
Dielectric Constant ◽  
Thermodynamic Stability ◽  
Thermodynamic Data ◽  
Gate Dielectric ◽  
Inorganic Compounds ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Binary Oxides ◽  
High K ◽  
Ranked List

ABSTRACTHigh K (dielectric constant) and silicon-compatibility are essential for an alternative gate dielectric for use in silicon MOSFETs. Thermodynamic data were used to comprehensively evaluate the thermodynamic stability of binary oxides and binary nitrides in contact with silicon at 1000 K. Using the Clausius-Mossotti equation and ionic polarizabilities, the K of all known inorganic compounds composed of Si-compatible binary oxides was estimated. A ranked list of alternate gate oxide candidates that are likely to possess both high K and silicon-compatibility is given.

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