scholarly journals Performance of rc low encoding techniques for reducing coupling transitions

2018 ◽  
Vol 7 (4.20) ◽  
pp. 36
Author(s):  
Shavali. V ◽  
Dr. Sreerama Reddy G.M ◽  
Dr. Ramana Reddy.P
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Propagation Delay ◽  
Total Power ◽  
Switching Activity ◽  
Dynamic Power ◽  
Delay Propagation ◽  
Total Power Consumption ◽  
Simulation Results ◽  
Data Buses

RC Network has delay propagation by wire and dynamic power dissipation. Basically it can perform two encoding techniques. They are Firstly it will reduce more dynamic power dissipation and delay propagation of wire simultaneously. Its simulation results of coupling activity  and switching activity is more when the input is in Toggle state on 8-bit  and for  32-bit data buses It increases. To reduce dynamic power is bus and total propagation delay  the encoding techniques is Introduced which reduces coupling Coupling transitions, Dynamic power. Secondly it will also reduce more total power consumption when Width of Bus and Length of Bits Increases Its coupling activity is Reduced Gradually when the Data moves for one state to another State and switching activity is Reduced  

scholarly journals A CLASS OF IRREDUNDANT ENCODING TECHNIQUES FOR REDUCING BUS POWER

2002 ◽  
Vol 11 (05) ◽  
pp. 445-457 ◽  
Author(s):  
YAZDAN AGHAGHIRI ◽  
FARZAN FALLAH ◽  
MASSOUD PEDRAM
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Total Power ◽  
Switching Activity ◽  
Printed Circuit ◽  
Memory Address ◽  
Total Power Consumption ◽  
Bus Encoding

This paper proposes a number of encoding techniques for decreasing power dissipation on global buses. The best target for these techniques is a wide and highly capacitive memory bus. Switching activity of the bus is reduced by means of encoding the values that are conveyed over them. More precisely, three irredundant bus-encoding techniques are presented in this paper. These techniques decrease the bus activity by as much as 86% for instruction addresses without the need to add redundant bus lines. Having no redundancy means that exercising these techniques on any existing system does not require redesign and remanufacturing of the printed circuit board of the system. The power dissipation of the encoder and decoder blocks is insignificant in comparison with the power saved on the memory address bus. This makes these techniques capable of reducing the total power consumption.

Implement Multichannel Fractional Sample Rate Convertor using Genetic Algorithm

2017 ◽  
Vol 8 (2) ◽  
pp. 10-21
Author(s):  
Vivek Jain ◽  
Navneet Agrawal
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Hamming Distance ◽  
Finite Impulse Response ◽  
Total Power ◽  
Dynamic Power ◽  
Total Power Consumption ◽  
Cmos Transistor ◽  
Sample Rate ◽  
Main Component

In this paper reduce power of multichannel fractional sample rate convertor by minimized hamming distance between consecutive coefficients of filter using Genetic algorithm. The main component of multichannel fractional sample rate convertor is Cascaded multiple architecture finite impulse response filter (CMFIR filter). CMFIR is implemented by cascading of cascaded integrator-comb (CIC) & multiply accumulate architecture (MAC) FIR filter. Genetic algorithm minimizes the hamming distance between consecutive coefficients of CMFIR filter. By Minimizing the hamming distance of consecutive filter coefficient reduces the transaction from 0 to 1 or 1 to 0. These techniques reduce the switching activity of CMOS transistor which is directly reduces Dynamic power consumption by multichannel sample rate convertor, it also minimizes the total power consumption of multichannel fractional sample rate convertor. later than use genetic algorithm on 1 to 128 channel Down sample rate convertor total power reduced by 3.44% to 61.56%, dynamic power reduced by 9.09% to 56.25% .1 to 128 channel Up sample rate convertor total power reduced by 2.81% to 45.42%, dynamic power reduced by 4.76% to 56%, 1 to 128 channel fractional sample rate convertor total power reduced by 1.44% to 17.17%, dynamic power reduced by 6.25% to 19.92%.

A Simplified Design Methodology for MOSFET-Only Wideband Mixer

2011 ◽  
Vol 57 (4) ◽  
pp. 503-509 ◽  
Author(s):  
Eduardo Ortigueira ◽  
Ivan Bastos ◽  
Luís Oliveira ◽  
Joăo Oliveira ◽  
Joăo Goes
Keyword(s):  
Power Consumption ◽  
Design Methodology ◽  
Noise Figure ◽  
Voltage Drop ◽  
Total Power ◽  
Dc Voltage ◽  
Total Power Consumption ◽  
Simulation Results ◽  
Medical Telemetry ◽  
Peak Gain

A Simplified Design Methodology for MOSFET-Only Wideband MixerIn this paper we present a MOSFET-only implementation of a wideband Gilbert Cell. The circuit uses a commongate topology for a wideband input match, capable to cover the Wireless Medical Telemetry Service (WMTS) frequency bands of 600 MHz and 1.4 GHz. In this circuit the load resistors are replaced by transistors in triode region, to reduce area and cost, and minimize the effects of process and supply variations and mismatches. In addition, we obtain a higher gain for the same DC voltage drop, with a reduced impact on the noise figure (NF). The performance of this topology is compared with that of a conventional mixer with load resistors. Simulation results show that a peak gain of 20.6 dB (about 6 dB improvement) and a NF about of 11 dB for the 600 MHz band. The total power consumption is 3.6 mW from a 1.2 V supply.

POWER REDUCTION TECHNIQUE USING MULTIPLE SUPPLY VOLTAGE AND SWITCHING ACTIVITY ANALYSIS

2013 ◽  
Vol 22 (02) ◽  
pp. 1250079
Author(s):  
BASHAR HADDAD ◽  
AMIN JARRAH
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Critical Path ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Activity Analysis ◽  
Vlsi Circuits ◽  
Total Power ◽  
Switching Activity ◽  
Activity Factor

Recent demand for low power VLSI circuits has been pushing the development of innovative approaches to reduce power dissipation. Supply voltage (V CC ) and switching activity factor (α) are main sources of dynamic power dissipation in CMOS technology. Furthermore, the power dissipation increases exponentially by the value of supply voltage. New approach based on switching activity analysis and multiple supply voltage is implemented successfully in logical circuits, taking in mind the critical path(s) of the design and switching activity factor of each element in the design. High supply voltage is applied on elements on the critical path(s). Elements off the critical path(s) are classified into categories according to their switching activity factors. The total power dissipation is reduced, while the propagation delay remains without any increase. The proposed approach combines the concepts of critical/non-critical paths and switching activity analysis to assign different V CCs to different elements.

Instruction Format Design for Low Power Embedded Systems

2015 ◽  
Vol 789-790 ◽  
pp. 829-832
Author(s):  
Jong Hee M. Youn ◽  
Dae Jin Park ◽  
Jeong Hun Cho ◽  
Doo San Cho
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Digital Circuit ◽  
Total Power ◽  
Switching Activity ◽  
Design Constraint ◽  
Instruction Fetch ◽  
Total Power Consumption ◽  
Instruction Format

Embedded systems demand to take high performance while executing on batteries. In such environment, the systems must be optimized with available technique to reduce energy consumption while not sacrificing performance. Especially, in mobile devices, power consumption is an important design constraint. Switching activity accounts for over 90% of total power consumption in a digital circuit. In this paper, we describe an approach to design instruction format for low power instruction fetch. The proposed method reduces switching activity of the instruction fetch logic by using a heuristic that minimizes switching between adjacent instructions. To do this, the proposed approach encodes opcodes so that frequently executed instruction pairs have smaller bit changes.

A Simple Fully Controllable Schmitt Trigger with Electronic Method Using VDTA

2015 ◽  
Vol 781 ◽  
pp. 180-183 ◽  
Author(s):  
Montree Siripruchyanun ◽  
Pracharat Satthaphol ◽  
Kangwal Payakkakul
Keyword(s):  
Power Consumption ◽  
Schmitt Trigger ◽  
Total Power ◽  
Pspice Simulation ◽  
Voltage Difference ◽  
Transconductance Amplifier ◽  
Total Power Consumption ◽  
Electronic Method ◽  
Simulation Results ◽  
Supply Voltages

A simple Schmitt trigger employing single VDTA (Voltage Difference Transconductance Amplifier) and one grounded resistor is proposed. The feature of the proposed Schmitt trigger is that its output hysteresis and amplitude can be independently adjusted. The PSpice simulation results are disclosed, it agrees well with the theoretical anticipation. The total power consumption approximately 443µW at ±1.5V supply voltages.

scholarly journals Dynamic Power Optimization of 32 Bit MIPS Processor Using Clock Gating For Low Power Applications

2019 ◽  
Vol 8 (2) ◽  
pp. 5936-5941
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Design ◽  
Total Power ◽  
Battery Life ◽  
Clock Gating ◽  
Dynamic Power ◽  
Total Power Consumption ◽  
Static Power ◽  
Major Factors

The demand for low power processor is increasing day by day in mobile application for video, audio, mixed signal processing, gaming console and battery-operated electronic devices. Power consumption is the main issue in batter operated devices which constantly reduces battery life. Compared to static power Dynamic power yields more power consumption in digital design. Clock power is one of the major factors in total power consumption which results in high dynamic power consumption. In this paper, a 32-bit MIPS processor is designed to maximize the performance while considering the battery life of the device. Clock gating and data gating method is adopted in this paper and to reduce dynamic power. This design is implemented on 28nm kintex-7 FPGA Board and power is analyzed

scholarly journals Efficient Operation Method of Aquifer Thermal Energy Storage System Using Demand Response

Energies ◽  
2021 ◽  
Vol 14 (11) ◽  
pp. 3129
Author(s):  
Jewon Oh ◽  
Daisuke Sumiyoshi ◽  
Masatoshi Nishioka ◽  
Hyunbae Kim
Keyword(s):  
Energy Storage ◽  
Power Consumption ◽  
Thermal Energy ◽  
Demand Response ◽  
Thermal Energy Storage ◽  
Heat Storage ◽  
Storage System ◽  
Total Power ◽  
Operation Method ◽  
Total Power Consumption

The mass introduction of renewable energy is essential to reduce carbon dioxide emissions. We examined an operation method that combines the surplus energy of photovoltaic power generation using demand response (DR), which recognizes the balance between power supply and demand, with an aquifer heat storage system. In the case that predicts the occurrence of DR and performs DR storage and heat dissipation operation, the result was an operation that can suppress daytime power consumption without increasing total power consumption. Case 1-2, which performs nighttime heat storage operation for about 6 h, has become an operation that suppresses daytime power consumption by more than 60%. Furthermore, the increase in total power consumption was suppressed by combining DR heat storage operation. The long night heat storage operation did not use up the heat storage amount. Therefore, it is recommended to the heat storage operation at night as much as possible before DR occurs. In the target area of this study, the underground temperature was 19.1 °C, the room temperature during cooling was about 25 °C and groundwater could be used as the heat source. The aquifer thermal energy storage (ATES) system in this study uses three wells, and consists of a well that pumps groundwater, a heat storage well that stores heat and a well that used heat and then returns it. Care must be taken using such an operation method depending on the layer configuration.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

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