Instruction Format Design for Low Power Embedded Systems

2015 ◽  
Vol 789-790 ◽  
pp. 829-832
Author(s):  
Jong Hee M. Youn ◽  
Dae Jin Park ◽  
Jeong Hun Cho ◽  
Doo San Cho
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Digital Circuit ◽  
Total Power ◽  
Switching Activity ◽  
Design Constraint ◽  
Instruction Fetch ◽  
Total Power Consumption ◽  
Instruction Format

Embedded systems demand to take high performance while executing on batteries. In such environment, the systems must be optimized with available technique to reduce energy consumption while not sacrificing performance. Especially, in mobile devices, power consumption is an important design constraint. Switching activity accounts for over 90% of total power consumption in a digital circuit. In this paper, we describe an approach to design instruction format for low power instruction fetch. The proposed method reduces switching activity of the instruction fetch logic by using a heuristic that minimizes switching between adjacent instructions. To do this, the proposed approach encodes opcodes so that frequently executed instruction pairs have smaller bit changes.

scholarly journals Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1429 ◽  
Author(s):  
Jin-Fa Lin ◽  
Cheng-Yu Chan ◽  
Shao-Wei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Full Adder ◽  
Total Power ◽  
Iot Applications ◽  
Delay Cell ◽  
Total Power Consumption ◽  
Array Multiplier ◽  
Cell Circuit

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

scholarly journals Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3649
Author(s):  
Minhyun Jin ◽  
Hyeonseob Noh ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Power Consumption ◽  
Edge Detection ◽  
Low Power ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

FLOORPLAN DESIGN WITH LOW POWER CONSIDERATIONS

1996 ◽  
Vol 07 (02) ◽  
pp. 305-322
Author(s):  
KAI-YUAN CHAO ◽  
D. F. WONG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Design ◽  
Network Size ◽  
Total Power ◽  
Wire Length ◽  
Performance Requirements ◽  
Total Power Consumption ◽  
Distribution Of Power ◽  
The Cost

In this paper, a floorplanner for low power design is presented. Our objective is to optimize total power consumption and area during the selection and placement of various implementations for circuit modules. Furthermore, the proposed method considers performance requirements, power line noises, and distribution of power consumption in order to generate lower and evenly distributed power dissipation over the resulting circuit floorplan with a specified performance. For a set of benchmark circuits we tested, on the average, our floorplanner can achieve decreases of total power consumption, wire-length, and power/ground network size by 18.3%, 4.6%, and 24%, respectively, at the cost of an area increase of 8.8% when compared with an existing area/wire-length driven floorplanner.

scholarly journals A Hardware Approach of a Low-Power IoT Communication Interface by NXP FlexIO Module

2019 ◽  
Vol 25 (6) ◽  
pp. 35-39
Author(s):  
Libor Chrastecky ◽  
Jaromir Konecny ◽  
Martin Stankus ◽  
Michal Prauzek
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Total Power ◽  
Processing Unit ◽  
Embedded Devices ◽  
Communication Interface ◽  
Result Section ◽  
Central Processing ◽  
Total Power Consumption ◽  
Software And Hardware

This article describes implementation possibilities of specialized microcontroller peripherals, as hardware solution for Internet of Things (IoT) low-power communication, interfaces. In this contribution, authors use the NXP FlexIO periphery. Meanwhile, RFC1662 is used as a reference communication standard. Implementation of RFC1662 is performed by software and hardware approaches. The total power consumption is measured during experiments. In the result section, authors evaluate a time-consumption trade-off between the software approach running in Central Processing Unit (CPU) and hardware implementation using NXP FlexIO periphery. The results confirm that the hardware-based approach is effective in terms of power consumption. This method is applicable in IoT embedded devices.

scholarly journals CMOS Operational Floating Current Conveyor Circuit for Instrumentation Amplifier Application

2020 ◽  
pp. 317-323
Author(s):  
Fahmi Elsayed ◽  
◽  
Mostafa Rashdan ◽  
Mohammad Salman
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Current Conveyor ◽  
Total Power ◽  
Low Power Consumption ◽  
Instrumentation Amplifier ◽  
Fully Integrated ◽  
Total Power Consumption ◽  
High Bandwidth ◽  
Operational Floating Current Conveyor

This paper presents a fully integrated CMOS Operational Floating Current Conveyor (OFCC) circuit. The proposed circuit is designed for instrumentation amplifier circuits. The CMOS OFCC circuit is designed and simulated using Cadence in TSMC 90 m technology kit. The circuit aims at two different design goals. The first goal is to design a low power consumption circuit (LBW design) while the second is to design a high bandwidth circuit (HBW design). The total power consumption of the LBW design is 1.26 mW with 30 MHz bandwidth while the power consumption of the HBW design is 3 mW with 104.6 MHz bandwidth.

scholarly journals A Low Power Sigma-Delta Modulator with Hybrid Architecture

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5309
Author(s):  
Shengbiao An ◽  
Shuang Xia ◽  
Yue Ma ◽  
Arfan Ghani ◽  
Chan Hwang See ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Total Power ◽  
Cmos Process ◽  
Hybrid Architecture ◽  
Sigma Delta Modulator ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Total Power Consumption

Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

scholarly journals Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

2021 ◽  
Author(s):  
Aswini Valluri ◽  
◽  
Sarada Musala ◽  
Muralidharan Jayabalan ◽  
◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Cmos Technology ◽  
Total Power ◽  
Silicon Area ◽  
Transmission Gate ◽  
Read Operation ◽  
Sram Cell ◽  
Total Power Consumption

There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

scholarly journals A CLASS OF IRREDUNDANT ENCODING TECHNIQUES FOR REDUCING BUS POWER

2002 ◽  
Vol 11 (05) ◽  
pp. 445-457 ◽  
Author(s):  
YAZDAN AGHAGHIRI ◽  
FARZAN FALLAH ◽  
MASSOUD PEDRAM
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Total Power ◽  
Switching Activity ◽  
Printed Circuit ◽  
Memory Address ◽  
Total Power Consumption ◽  
Bus Encoding

This paper proposes a number of encoding techniques for decreasing power dissipation on global buses. The best target for these techniques is a wide and highly capacitive memory bus. Switching activity of the bus is reduced by means of encoding the values that are conveyed over them. More precisely, three irredundant bus-encoding techniques are presented in this paper. These techniques decrease the bus activity by as much as 86% for instruction addresses without the need to add redundant bus lines. Having no redundancy means that exercising these techniques on any existing system does not require redesign and remanufacturing of the printed circuit board of the system. The power dissipation of the encoder and decoder blocks is insignificant in comparison with the power saved on the memory address bus. This makes these techniques capable of reducing the total power consumption.

scholarly journals A New Multi-Bit Flip-Flop Merging Mechanism for Power Consumption Reduction in the Physical Implementation Stage of ICs Conception

2019 ◽  
Vol 9 (1) ◽  
pp. 3
Author(s):  
Lekbir Cherif ◽  
Mohamed Chentouf ◽  
Jalal Benallal ◽  
Mohammed Darmi ◽  
Rachid Elgouri ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Negative Impact ◽  
Optimization Technique ◽  
Total Power ◽  
Flip Flop ◽  
Physical Implementation ◽  
Total Power Consumption ◽  
Bit Flip ◽  
Implementation Stage

Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such an optimization method are high performance, low power usage and small area (PPA). Therefore, any new optimization technique should improve at least one, if not all, of these requirements. This paper proposes a new low-power methodology, applying a MBFF merging solution during the physical implementation of an IC to achieve better power consumption and area reduction. The aim of this study is to prove the benefit of this methodology on the power saving capability of the system while demonstrating that the proposed methodology does not have a negative impact on the circuit performance and design routability. The experimental results show that MBFF merging of 76% can be achieved and preserved throughout the entire physical implementation process, from cell placement to the final interconnection routing, without impacting the system’s performance or routability. Moreover, the clock wirelength, nets and buffers needed to balance the clock network were reduced by 11.98%, 3.82% and 9.16%, respectively. The reduction of the clock tree elements led to a reduction of the power consumption of the clock nets, registers and cells by 22.11%, 20.84% and 12.38%, respectively. The total power consumption of the design was reduced by 2.67%.

scholarly journals LOW POWER SI-BASED POWER AMPLIFIER FOR HEALTHCARE APPLICATION

2016 ◽  
Vol 8 (9) ◽  
pp. 307 ◽  
Author(s):  
Wei Cai ◽  
Cheng Li ◽  
Heng Gu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Amplifier ◽  
Process Variations ◽  
Cmos Technology ◽  
Total Power ◽  
Power Added Efficiency ◽  
Trade Offs ◽  
Total Power Consumption ◽  
Class B

<p><strong>Objective: </strong>The objective of this research was to design a 2.4 GHz class B Power Amplifier (PA), with 0.18um Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence software, for health care applications. The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design.</p><p><strong>Methods: </strong>This paper introduces the design of a 2.4GHz class B power amplifier designed as dual gate topology. This class B power amplifier could transmit 26dBm output power to a 50Ω load. The power added efficiency was 60% minimum and the power gain was 90dB, the total power consumption was 6.9 mW.</p><p><strong>Results:</strong> Besides, accurate device modeling, is needed, due to the leakage and process variations.</p><p><strong>Conclusion</strong>:<strong> </strong>The performance of the power amplifier meets the specification requirements of the desired.</p>

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