POWER REDUCTION TECHNIQUE USING MULTIPLE SUPPLY VOLTAGE AND SWITCHING ACTIVITY ANALYSIS

2013 ◽  
Vol 22 (02) ◽  
pp. 1250079
Author(s):  
BASHAR HADDAD ◽  
AMIN JARRAH
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Critical Path ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Activity Analysis ◽  
Vlsi Circuits ◽  
Total Power ◽  
Switching Activity ◽  
Activity Factor

Recent demand for low power VLSI circuits has been pushing the development of innovative approaches to reduce power dissipation. Supply voltage (V CC ) and switching activity factor (α) are main sources of dynamic power dissipation in CMOS technology. Furthermore, the power dissipation increases exponentially by the value of supply voltage. New approach based on switching activity analysis and multiple supply voltage is implemented successfully in logical circuits, taking in mind the critical path(s) of the design and switching activity factor of each element in the design. High supply voltage is applied on elements on the critical path(s). Elements off the critical path(s) are classified into categories according to their switching activity factors. The total power dissipation is reduced, while the propagation delay remains without any increase. The proposed approach combines the concepts of critical/non-critical paths and switching activity analysis to assign different V CCs to different elements.

scholarly journals Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

2021 ◽  
Vol 2089 (1) ◽  
pp. 012080
Author(s):  
M. Srinivas ◽  
K.V. Daya Sagar
Keyword(s):  
Energy Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Battery Life

Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

scholarly journals Estimation of Leakage Power and Delay in CMOS Circuits

2020 ◽  
Vol 4 (7) ◽  
pp. 14-19
Author(s):  
Mohasinul Huq N Md ◽  
Mohan Das S ◽  
Bilal N Md
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Leakage Power ◽  
Nand Gate ◽  
High Threshold ◽  
Cmos Circuits ◽  
Low Leakage

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

scholarly journals Power Efficient VLSI Inverter Design using Adiabatic Logic and Estimation of Power dissipation using VLSI-EDA Tool

2012 ◽  
pp. 155-158
Author(s):  
Samik Samanta
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Vlsi Circuits ◽  
Limiting Factor ◽  
Switching Activity ◽  
Cmos Inverter ◽  
Power Efficient ◽  
Adiabatic Switching ◽  
Adiabatic Logic ◽  
Innovative Solutions

Power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high complexity of VLSI systems used in various applications, the power dissipation in CMOS inverter, arises from it’s switching activity, which is mainly influenced by the supply voltage and effective capacitance.[1,2,3] To optimize power dissipation, the researches show various techniques like appropriate coding, appropriate design architectures, appropriate manipulation algorithms. In this paper we have applied adiabatic logic design approach to design COMS inverter. Adiabatic switching techniques based on energy recovery principle are one of the innovative solutions at a circuit and logic level achieve reduction in power [12] Various adiabatic logic based inverters are shown. Mainly our aim is to design and simulate PFAL inverters. Finally we have calculated dissipated power of static CMOS inverter and compare it with that of PFAL based inverter. [4, 6]

scholarly journals Performance of rc low encoding techniques for reducing coupling transitions

2018 ◽  
Vol 7 (4.20) ◽  
pp. 36
Author(s):  
Shavali. V ◽  
Dr. Sreerama Reddy G.M ◽  
Dr. Ramana Reddy.P
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Propagation Delay ◽  
Total Power ◽  
Switching Activity ◽  
Dynamic Power ◽  
Delay Propagation ◽  
Total Power Consumption ◽  
Simulation Results ◽  
Data Buses

RC Network has delay propagation by wire and dynamic power dissipation. Basically it can perform two encoding techniques. They are Firstly it will reduce more dynamic power dissipation and delay propagation of wire simultaneously. Its simulation results of coupling activity  and switching activity is more when the input is in Toggle state on 8-bit  and for  32-bit data buses It increases. To reduce dynamic power is bus and total propagation delay  the encoding techniques is Introduced which reduces coupling Coupling transitions, Dynamic power. Secondly it will also reduce more total power consumption when Width of Bus and Length of Bits Increases Its coupling activity is Reduced Gradually when the Data moves for one state to another State and switching activity is Reduced  

scholarly journals Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications

2020 ◽  
Vol 14 (05) ◽  
pp. 73 ◽  
Author(s):  
T. Suguna ◽  
M. Janaki Rani
Keyword(s):  
Mobile Applications ◽  
Supply Voltage ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Switching Activity ◽  
Ripple Carry Adder ◽  
Adiabatic Logic ◽  
Overall Performance ◽  
Power Delay Product ◽  
Research Domain

In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL styles. Moreover in this paper, 32 bit adders such as Ripple Carry Adder (RCA), Carry Select Adder (CSLA), Carry Save Adder (CSA), Carry Skip Adder (CSKA) and Brent Kung Adder (BKA) are realised using proposed ECRL and 2PASCL adiabatic full adders. All the adders are implemented and simulated using TANNER EDA tool 22nm technology, parameters like power, area, delay and power delay product (PDP) of all the adders are observed at different operating frequencies, with supply voltage of 0.95 v and load capacitance of 0.5 pF. The observed parameters are compared with the existing adiabatic full adder designs and concluded that the proposed adiabatic full adders have the advantages of less power, delay and transistor count. In conclusion ECRL full adder is 31% faster, has equal PDP and less area than 2PASCL full adder. At 1000MHz ECRL 32 bit carry save adder is having less delay among all the 32 bit adder and 65% less PDP than 2PASCL adder and it is concluded that ECRL 32 bit carry save adder can be selected for implementation of circuits that can be used in portable mobile applications.

scholarly journals Floating Active Inductor Based Trans-Impedance Amplifier in 0.18 μm CMOS Technology for Optical Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1547
Author(s):  
Xiangyu Chen ◽  
Yasuhiro Takahashi
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chip Area ◽  
Active Inductors ◽  
Low Pass ◽  
Optical Applications ◽  
Fifth Order

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI circuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration, the broadband matching network, and the regulated cascode input stage to enhance the bandwidth and gain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is implemented using 0.18 μ m Rohm CMOS technology and consumes only 10.7 mW with a supply voltage of 1.8 V. When used with a 150 fF photodiode capacitance, it exhibits the following characteristics: gain of 41 dB Ω and −3 dB frequency of 10 GHz. This TIA occupies an area of 180 μ m × 118 μ m.

scholarly journals Low Power VLSI Design Techniques: A Review

2021 ◽  
Vol 23 (11) ◽  
pp. 172-183
Author(s):  
Ketan J. Raut ◽  
◽  
Abhijit V. Chitre ◽  
Minal S. Deshmukh ◽  
Kiran Magar ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Optimization Techniques ◽  
Battery Life ◽  
Dynamic Power ◽  
Cmos Vlsi

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator on Flexible Hardware for a Flash ADC

2019 ◽  
Vol 29 (05) ◽  
pp. 2050073
Author(s):  
Ashima Gupta ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Total Power ◽  
Clock Frequency ◽  
Voltage Comparator ◽  
Flash Adc ◽  
Differential Voltage ◽  
Place And Route ◽  
Eda Tools

A 4-bit flash ADC utilizing the advantage of digital-based differential voltage comparator is presented in this paper. This circuit has an advantage of digital circuit concept and can be easily migrated to lower technologies. Also, the digital circuits are less sensitive to the noise and device mismatches can be synthesized and auto place and route (P&R) using EDA tools. The design of the proposed comparator is based on the standard cells implementation. As the proof of concept this comparator is implemented on Xilinx Basys-3 Artix-7 FPGA kit. The prototype of complete 4-bit Flash ADC is designed in 180[Formula: see text]nm CMOS technology with 1.8[Formula: see text]V supply voltage. The measured values of ENOB, SNDR, SNR and SFDR are 3.6, 23.43[Formula: see text]dB, 25.2[Formula: see text]dB and 30.1[Formula: see text]dB, respectively at 33.20[Formula: see text]MHz input frequency and 200[Formula: see text]MHz clock frequency. The total power consumed by the 4-bit flash ADC is 2.14[Formula: see text]mW. The calculated value of DNL and INL is [Formula: see text] LSB and [Formula: see text] LSB respectively.

High-Swing, High-Resolution, Low-Power, Low-Area Voltage-Mode LTA/WTA Circuits

2015 ◽  
Vol 24 (07) ◽  
pp. 1550103 ◽  
Author(s):  
Mohammad Soleimani ◽  
Siroos Toofan ◽  
Mostafa Yargholi
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Rank Order ◽  
Active Area ◽  
Total Power ◽  
Common Source ◽  
Cmos Process ◽  
Process Technology

In this paper, a general architecture for analog implementation of loser/winner-take-all (LTA/WTA) and other rank order circuits is presented. This architecture is composed of a differential amplifier with merged n-inputs and a merged common-source with active load (MCSAL) circuit to choose the desired input. The advantages of the proposed structure are simplicity, very high resolution, very low supply voltage requirements, very low output resistor, low power dissipation, low active area and simple expansion for multiple inputs by adding only three transistors for each extra input. The post-layout simulation results of proposed circuits are presented by HSPICE software in 0.35-μm CMOS process technology. The total power dissipation of proposed circuits is about 110-μW. Also, the total active area is about 550-μm2 for five-input proposed circuits, and would be negligibly increased for each extra input.

scholarly journals 60 GHz Front-End Components for Broadband Wireless Communication in 130 nm CMOS Technology

2016 ◽  
Vol 21 (1) ◽  
pp. 67-77
Author(s):  
Vasilis Kolios ◽  
Konstantinos Giannakidis ◽  
Grigorios Kalivas
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Spectral Space ◽  
60 Ghz ◽  
Front End ◽  
Total Power Consumption ◽  
5 Ghz

Abstract The over 5 GHz available spectral space allocated worldwide around the 60 GHz band, is very promising for very high data rate wireless short-range communications. In this article we present two key components for the 60 GHz front-end of a transceiver, in 130 nm RF CMOS technology: a single-balanced mixer with high Conversion Gain (CG), reduced Noise Figure (NF) and low power consumption, and an LC cross-coupled Voltage Controlled Oscillator (VCO) with very good linearity, with respect to Vctrl, and very low Phase Noise (PN). In both circuits, custom designed inductors and a balun structure for the mixer are employed, in order to enhance their performance. The VCO’s inductor achieves an inductance of 198 pH and a quality factor (Q) of 30, at 30 GHz. The balun shows less than 1o Phase Imbalance (PI) and less than 0.2 dB Amplitude Imbalance (AI), from 57 to 66 GHz. The mixer shows a CG greater than 15 dB and a NF lower than 12 dB. In addition, the VCO achieves a Phase Noise lower than -106 dBc/Hz at 1 MHz offset, and shows great linearity for the entire band. Both circuits are biased with a 1.2 V supply voltage and the total power consumption is about 10.6 mW for the mixer and 10.92 mW for the VCO.

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