scholarly journals Low-power low-area techniques for multichannel recording circuits dedicated to biomedical experiments

2016 ◽  
Vol 64 (3) ◽  
pp. 615-624 ◽  
Author(s):  
P. Kmon
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Silicon Area ◽  
Multichannel Recording ◽  
Low Area ◽  
Wide Range ◽  
Recording Channels ◽  
Recording Channel ◽  
Digital Circuitry

Abstract This paper presents techniques introduced to minimize both power and silicon area of the multichannel integrated recording circuits dedicated to biomedical experiments. The proposed methods were employed in multichannel integrated circuit fabricated in CMOS 180nm process and were validated with the use of a wide range of measurements. The results show that both a single recording channel and correction blocks occupy about 0.061 mm2 of the area and consume only 8.5 μW of power. The input referred noise is equal to 4.6 μVRMS. With the use of additional digital circuitry, each of the recording channels may be independently configured. The lower cut-off frequency may be set within the range of 0.1 Hz–700 Hz, while the upper cut-off frequency, depending on the recording mode chosen, can be set either to 3 kHz/13 kHz or may be tuned in the 2 Hz–400 Hz range. The described methods were introduced in the 64-channel integrated circuit. The key aspect of the proposed design is the fact that proposed techniques do not limit functionality of the system and do not deteriorate its overall parameters.

scholarly journals New First-Order Secure AES Performance Records

2021 ◽  
pp. 304-327
Author(s):  
Aein Rezaei Shahmirzadi ◽  
Dušan Božilov ◽  
Amir Moradi
Keyword(s):  
Integrated Circuit ◽  
State Of The Art ◽  
Large Set ◽  
First Order ◽  
Low Area ◽  
Wide Range ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Application Specific Integrated Circuit ◽  
The Cost

Being based on a sound theoretical basis, masking schemes are commonly applied to protect cryptographic implementations against Side-Channel Analysis (SCA) attacks. Constructing SCA-protected AES, as the most widely deployed block cipher, has been naturally the focus of several research projects, with a direct application in industry. The majority of SCA-secure AES implementations introduced to the community opted for low area and latency overheads considering Application-Specific Integrated Circuit (ASIC) platforms. Albeit a few, those which particularly targeted Field Programmable Gate Arrays (FPGAs) as the implementation platform yield either a low throughput or a not-highly secure design.In this work, we fill this gap by introducing first-order glitch-extended probing secure masked AES implementations highly optimized for FPGAs, which support both encryption and decryption. Compared to the state of the art, our designs efficiently map the critical non-linear parts of the masked S-box into the built-in Block RAMs (BRAMs).The most performant variant of our constructions accomplishes five first-order secure AES encryptions/decryptions simultaneously in 50 clock cycles. Compared to the equivalent state-of-the-art designs, this leads to at least 70% reduction in utilization of FPGA resources (slices) at the cost of occupying BRAMs. Last but not least, we provide a wide range of such secure and efficient implementations supporting a large set of applications, ranging from low-area to high-throughput.

scholarly journals Low-power ASIC suitable for miniaturized wireless EMG systems

2019 ◽  
Vol 70 (5) ◽  
pp. 393-399 ◽  
Author(s):  
Vilem Kledrowetz ◽  
Roman Prokop ◽  
Lukas Fujcik ◽  
Michal Pavlik ◽  
Jiří Háze
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Low Voltage ◽  
Cmos Technology ◽  
Instrumentation Amplifier ◽  
Pass Filter ◽  
Delta Sigma ◽  
Pulse Density ◽  
Wide Range

Abstract Nowadays, the technology advancements of signal processing, low-voltage low-power circuits and miniaturized circuits have enabled the design of compact, battery-powered, high performance solutions for a wide range of, particularly, biomedical applications. Novel sensors for human biomedical signals are creating new opportunities for low weight wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents the design and implementation of a novel miniaturized low-power sensor in integrated circuit (IC) form suitable for wireless electromyogram (EMG) systems. Signal inputs (electrodes) are connected to this application-specific integrated circuit (ASIC). The ASIC consists of several consecutive parts. Signals from electrodes are fed to an instrumentation amplifier (INA) with fixed gain of 50 and filtered by two filters (a low-pass and high-pass filter), which remove useless signals and noise with frequencies below 20 Hz and above 500 Hz. Then signal is amplified by a variable gain amplifier. The INA together with the reconfigurable amplifier provide overall gain of 50, 200, 500 or 1250. The amplified signal is then converted to pulse density modulated (PDM) signal using a 12-bit delta-sigma modulator. The ASIC is fabricated in TSMC0.18 mixed-signal CMOS technology.

Simple circuit for pacing hearts of experimental animals

1992 ◽  
Vol 262 (6) ◽  
pp. H1939-H1940 ◽  
Author(s):  
G. L. Freeman ◽  
J. T. Colston
Keyword(s):  
Integrated Circuit ◽  
Simple Circuit ◽  
Cardiovascular Research ◽  
Experimental Animals ◽  
Wide Range ◽  
Astable Multivibrator

In this paper we describe a simple pacing circuit which can be used to drive the heart over a wide range of rates. The circuit is an astable multivibrator, based on an LM555 integrated circuit. It is powered by a 9-V battery and is small enough for use in rabbits. The circuit is easily constructed and inexpensive, making it attractive for numerous applications in cardiovascular research.

scholarly journals Low Power Cusped Field Thruster Developed for the Space-Borne Gravitational Wave Detection Mission in China

2021 ◽  
Vol 11 (14) ◽  
pp. 6549
Author(s):  
Hui Liu ◽  
Ming Zeng ◽  
Xiang Niu ◽  
Hongyan Huang ◽  
Daren Yu
Keyword(s):  
Low Power ◽  
Gravitational Wave ◽  
Attitude Control ◽  
High Efficiency ◽  
Experimental Investigations ◽  
Attitude Control System ◽  
Gravitational Wave Detection ◽  
Wave Detection ◽  
Wide Range ◽  
Institute Of Technology

The microthruster is the crucial device of the drag-free attitude control system, essential for the space-borne gravitational wave detection mission. The cusped field thruster (also called the High Efficiency Multistage Plasma Thruster) becomes one of the candidate thrusters for the mission due to its low complexity and potential long life over a wide range of thrust. However, the prescribed minimum of thrust and thrust noise are considerable obstacles to downscaling works on cusped field thrusters. This article reviews the development of the low power cusped field thruster at the Harbin Institute of Technology since 2012, including the design of prototypes, experimental investigations and simulation studies. Progress has been made on the downscaling of cusped field thrusters, and a new concept of microwave discharge cusped field thruster has been introduced.

A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller

2021 ◽  
pp. 1-11
Author(s):  
Peng Yin ◽  
Zhou Shu ◽  
Yingjun Xia ◽  
Tianmei Shen ◽  
Xiao Guan ◽  
...  
Keyword(s):  
Low Power ◽  
Word Alignment ◽  
Low Area

scholarly journals Design of a high-stability heterogeneous clock system for small satellites in LEO

GPS Solutions ◽  
2021 ◽  
Vol 25 (3) ◽  
Author(s):  
Damon Van Buren ◽  
Penina Axelrad ◽  
Scott Palo
Keyword(s):  
Low Power ◽  
High Stability ◽  
Time Frame ◽  
System Stability ◽  
Small Satellite ◽  
Crystal Oscillator ◽  
Small Satellites ◽  
Clock System ◽  
Wide Range

AbstractWe describe our investigation into the performance of low-power heterogeneous timing systems for small satellites, using real GPS observables from the GRACE Follow-On mission. Small satellites have become capable platforms for a wide range of commercial, scientific and defense missions, but they are still unable to meet the needs of missions that require precise timing, on the order of a few nanoseconds. Improved low-power onboard clocks would make small satellites a viable option for even more missions, enabling radio aperture interferometry, improved radio occultation measurements, high altitude GPS navigation, and GPS augmentation missions, among others. One approach for providing improved small satellite timekeeping is to combine a heterogeneous group of oscillators, each of which provides the best stability over a different time frame. A hardware architecture that uses a single-crystal oscillator, one or more Chip Scale Atomic Clocks (CSACs) and the reference time from a GPS receiver is presented. The clocks each contribute stability over a subset of timeframes, resulting in excellent overall system stability for timeframes ranging from less than a second to several days. A Kalman filter is used to estimate the long-term errors of the CSACs based on the CSAC-GPS time difference, and the improved CSAC time is used to discipline the crystal oscillator, which provides the high-stability reference clock for the small satellite. Simulations using GRACE-FO observations show time error standard deviations for the system range from 2.3 ns down to 1.3 ns for the clock system, depending on how many CSACs are used. The results provide insight into the timing performance which could be achieved on small LEO spacecraft by a low power timing system.

scholarly journals Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 73
Author(s):  
Francesco Ratto ◽  
Tiziana Fanni ◽  
Luigi Raffo ◽  
Carlo Sau
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Systems Design ◽  
Hardware Acceleration ◽  
High Level Synthesis ◽  
Clock Gating ◽  
Technology Application ◽  
Positive Effects ◽  
High Level ◽  
Different Levels

With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

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