3D Process Integration – Wafer-to-Wafer and Chip-to-Wafer Bonding

2006 ◽  
Vol 970 ◽  
Author(s):  
Thorsten Matthias ◽  
Markus Wimplinger ◽  
Stefan Pargfrieder ◽  
Paul Lindner
Keyword(s):  
Wafer Bonding ◽  
Process Integration ◽  
Logic Device ◽  
Wafer Level ◽  
Integration Schemes ◽  
Research Level ◽  
Rf Devices ◽  
Manufacturing Technologies ◽  
The Individual ◽  
3D Chip Stacking

ABSTRACTMany feasibility and design studies during the last years have shown that devices based on 3D chip stacking and integration can significantly outperform traditional planar (2D) devices. Furthermore, as packaging of the devices is a major cost factor, the possibility to integrate multiple functional entities in one package offers a huge potential for cost reduction. On research level the technical feasibility has been proven for a variety of processes. Today's focus lies on innovative manufacturing technologies and process integration schemes, which meet both, the economic and the technical demands.Stacking of individual chips (both chip-to-wafer and wafer-to-wafer) has the inherent advantage that different functional subsystems like logic and memory can be processed on separate wafers thereby reducing the complexity and the number of process steps greatly. The individual chips can be processed on heterogeneous materials, in different fabs and by different producers.Wafer-level integration has the advantage of higher throughput, enhanced cleanliness and the flexibility that standard fab equipment can be used for further processing. 3D integration applying chip-to-wafer bonding focuses on the yield (“good known die”) and enables to stack dies of different size e.g. several small dies on one big base die. This allows e.g. the integration of a logic device from a 300mm Si wafer with RF devices from a 150mm GaAs wafer.In this paper a higher emphasis lies on the key enabling manufacturing technologies and supported processes.

Journey Toward Process Convergence in TSV Technology

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001282-001321
Author(s):  
Sesh Ramaswami ◽  
John Dukovic
Keyword(s):  
Process Integration ◽  
Semiconductor Industry ◽  
Rapid Development ◽  
Chemical Mechanical Planarization ◽  
Cost Effective ◽  
Superior Performance ◽  
Wafer Level ◽  
Unit Process ◽  
Integration Schemes ◽  
Process Convergence

Continuous demand for more advanced electronic devices with higher functionality and superior performance in smaller packages is driving the semiconductor industry to develop new and more advanced 3D wafer-level interconnect technologies involving TSVs (through-silicon vias). The TSVs are created either on full-thickness wafer from the wafer front-side ¡V as part of wafer-fab processing during Middle-Of-Line (¡§via middle¡¨) or Back-End-Of-Line (¡§via last BEOL¡¨) ¡V or from the wafer backside after wafer thinning (¡§via last backside¡¨). Independent of the specific approach, the main steps include via etching, lining with insulator, copper barrier/seed deposition, via fill, and chemical mechanical planarization (CMP). Over the past year, the industry has been converging toward some primary unit processes and integration schemes for creating the TSVs. A common cost-of-ownership framework has also begun to emerge. Active collaboration underway among equipment suppliers, materials providers and end users is bringing about rapid development and validation of cost-effective TSV technology in end products. This presentation will address unit-process and integration challenges of TSV fabrication in the context of 20x100ƒÝm and 5x50ƒÝm baseline process flows at Applied Materials. Highlights of wafer-backside process integration involving wafers bonded to silicon or glass carriers will also be discussed.

Patterned Permanent Bonding of Benzocyclobutene Based Dielectric Materials for Advanced Wafer Level Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000886-000912
Author(s):  
Jong-Uk Kim ◽  
Anupam Choubey ◽  
Rosemary Bell ◽  
Hua Dong ◽  
Michael Gallagher ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Dielectric Materials ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Integration Schemes ◽  
Device Reliability ◽  
Package Size ◽  
Microelectronics Industry ◽  
Improve Device ◽  
Joining Process

The microelectronics industry is being continually challenged to decrease package size, lower power consumption and improve device performance for the mobile communication and server markets. In order to keep pace with these requirements, device manufacturers and assembly companies are focused on developing 3D-TSV integration schemes that will require stacking of 50 um thinned wafers with gaps of 15 microns or less. While conventional underfill approaches have been demonstrated for chip to chip and chip to wafer schemes, new materials and processes are required for wafer to wafer bonding given the target bondline and wafer handling issues. Photopatternable, low temperature curable dielectrics offer a potential solution to solve the issues by eliminating the need for flow and material entrapment during the joining process. This should result in a simplified bonding process that enables wafer to wafer bonding with improved device reliability. In this work, we will focus on validating the critical steps including patterning and bonding that are required to demonstrate the utility of this process using an aqueous developable benzocyclobutene based photodielectric material.

The Role of Wafer Bonding in 3D Integration and Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000355-000360
Author(s):  
James Hermanowski ◽  
Greg George
Keyword(s):  
Wafer Bonding ◽  
Process Integration ◽  
3D Integration ◽  
3D Ic ◽  
Integration Schemes ◽  
Front End

There are numerous process integration schemes currently in place for the implementation of 3D-IC. Via first, via middle, via last along with back end of line (BEOL), front end of line (FEOL) and other variations of these approaches. This work will explore the role of wafer bonding, both permanent and temporary, in the fabrication of 3D-IC. Additionally, the materials and process flows used for these processes will be examined in detail.

Characterization of Unfilled Tungsten Plugs on a 0.35μm CMOS Multilevel Metallization Process

1996 ◽  
Author(s):  
H. Sur ◽  
S. Bothra ◽  
Y. Strunk ◽  
J. Hahn
Keyword(s):  
Process Development ◽  
Process Integration ◽  
Wafer Level ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Integration Approach ◽  
Intermetal Dielectric ◽  
Metallization Process ◽  
Section Analysis

Abstract An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

scholarly journals Coverage Layout Design Rules and Insertion Utilities for CMP-Related Processes

2020 ◽  
Vol 11 (1) ◽  
pp. 2
Author(s):  
Eitan N. Shauly ◽  
Sagee Rosenthal
Keyword(s):  
Integrated Circuit ◽  
Thermal Effects ◽  
Process Integration ◽  
Proximity Effects ◽  
Published Data ◽  
Metal Gate ◽  
Comprehensive Description ◽  
Advanced Technologies ◽  
High K ◽  
Rf Devices

The continuous scaling needed for higher density and better performance has introduced some new challenges to the planarity processes. This has resulted in new definitions of the layout coverage rules developed by the foundry and provided to the designers. In advanced technologies, the set of rules considers both the global and the local coverage of the front-end-of line (FEOL) dielectric layers, to the back-end-of-line (BEOL) Cu layers and Al layers, to support high-k/Metal Gate process integration. For advance technologies, a new set of rules for dummy feature insertion was developed by the integrated circuit (IC) manufacturers in order to fulfill coverage limits. New models and utilities for fill insertion were developed, taking into consideration the design coverage, thermal effects, sensitive signal line, critical analog and RF devices like inductors, and double patterning requirements, among others. To minimize proximity effects, cell insertion was also introduced. This review is based on published data from leading IC manufacturers with a careful integration of new experimental data accumulated by the authors. We aim to present a typical foundry perspective. The review provides a detailed description of the chemical mechanical polishing (CMP) process and the coverage dependency, followed by a comprehensive description of coverage rules needed for dielectric, poly, and Cu layers used in advanced technologies. Coverage rules verification data are then presented. RF-related aspects of some rules, like the size and the distance of dummy features from inductors, are discussed with additional design-for-manufacturing layout recommendations as developed by the industry.

High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing

2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Precision ◽  
Wafer Bonding ◽  
Wafer Level ◽  
3D Ics ◽  
Direct Wafer Bonding ◽  
Bonding Technology

(Invited) High Accuracy Aligned Wafer Bonding for Wafer-Level Integration

2018 ◽  
Vol 86 (5) ◽  
pp. 145-158 ◽  
Author(s):  
Thomas Plach ◽  
Bernhard Rebhan ◽  
Viorel Dragoi ◽  
Thomas Wagenleitner ◽  
Markus Wimplinger ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
High Accuracy ◽  
Wafer Level

scholarly journals Assessment of Impact of Capital Acquisitions on the Economic Situation of Consolidated Entities in the Czech Republic

2019 ◽  
Vol 67 (5) ◽  
pp. 1335-1345
Author(s):  
Jaroslava Rajchlová ◽  
Anna Fedorová ◽  
Kristina Somerlíková ◽  
Libor Grega
Keyword(s):  
Czech Republic ◽  
Synergistic Effects ◽  
Business Environment ◽  
Fundamental Aspect ◽  
Consolidated Financial Statements ◽  
The Czech Republic ◽  
Individual Assessment ◽  
Research Level ◽  
The Individual ◽  
Parent Companies

Business acquisition constitutes a fundamental aspect of business environment formation. Our research has focused on assessment of impact of capital acquisition on the economic condition of the company. Therefore, the second research level has been initiated, focusing on the individual assessment of the single companies to identify allocation of synergy between consolidated units and parent companies in the Czech Republic. For our research, taking into consideration availability of data and subsequent explanatory value of the results, we will consider synergistic effect as presented in the Ansoff’s concept. Consolidated financial statements of totally 719 groups of accounting entities – business concerns in the Czech Republic has been studied in the research. A composite indicator, as the modern tool for comparison and evaluation of development of entities, has been selected to compare individual economic indicators of parent companies and group of their companies. We believe that developed arguments allow us to formulate conclusion that capital acquisitions, resulting in the years 2008–2013 in the obligation to compile consolidated financial statement, have brought positive financial synergistic effects in majority of cases, and we can rank them among successful business activities.

Reliability estimation and failure mode prediction for 3D chip stacking package with the application of wafer-level underfill

2013 ◽  
Vol 107 ◽  
pp. 107-113 ◽  
Author(s):  
Chang-Chun Lee ◽  
Tsung-Fu Yang ◽  
Chih-Sheng Wu ◽  
Kuo-Shu Kao ◽  
Ren-Chin Cheng ◽  
...  
Keyword(s):  
Failure Mode ◽  
Reliability Estimation ◽  
Wafer Level ◽  
3D Chip Stacking

Evalulation of Electrodeposited Photoresists for use in the Fabrication of an Optochip Silicon Interposer

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001555-001595
Author(s):  
Cornelia Tsang ◽  
Janet Okada ◽  
Eric Huenger
Keyword(s):  
Printed Circuit Boards ◽  
Process Integration ◽  
Product Yield ◽  
Wafer Surface ◽  
Wafer Level ◽  
Design Elements ◽  
Conformal Coating ◽  
3D Packaging ◽  
Study Process ◽  
Negative Tone

As 3D packaging technology and designs evolve, increasing complexity has been introduced in the fabrication of these devices. The integration of optical devices along with electronic wired elements such as the package platform identified in image sensors is one prime example where the design elements of the structures significantly increase the topography on the surface of the system. This multiplies the degree of difficulty in the lithography solution chosen to facilitate fabrication of these structures. The use of electrodeposited (ED) photoresists is a technology platform that has been used in MEMs, printed circuit boards, backside vias, etc, and can play a significant role in enabling new 3D packaging solutions. In this research, the successful fabrication of an Optochip silicon interposer, which integrates electrical and optical components onto a single substrate with high density interconnection, was enabled through use of electrodeposited (ED) photoresist. The Optochip interposer was manufactured in a standard 200 mm semiconductor fab and this precipitated the process integration requirement of first etching “optical vias” into the silicon at wafer-level prior to the final lithography steps. As such, challenging topography was introduced into the system. A resist solution able to address the following conditions was required: 1) sufficient conformal coating into large optical vias measuring 150 um diameter by 200 um depth, 2) no resist pull-back over sharp 90 degree angle corners where the optical vias met the wafer surface, 3) ability to resolve 30 um diameter surface pads at 50 um pitch and 4) chemical resistance to Ni and cyanide-based Au plating baths. This presentation will discuss how various photoresists were examined that resulted in ED photoresist being chosen for the aforementioned application. Both negative-tone and positive-tone ED photoresists were considered. Experiments to study process parameters and environmental factors on product yield were performed using test wafers with optical vias. These experiments resulted in positive-tone ED photoresist being selected. Test wafers plated with NiAu resulted in ~ 90% process yield. The presentation will conclude by demonstrating the ability to achieve good yield on integrated product wafers.

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