The Behavior of Polysilicon Thin Film Stress and Structure Under Rapid Thermal Processing Conditions

1988 ◽  
Vol 130 ◽  
Author(s):  
Walter Huber ◽  
G. Borionetti ◽  
C. Villani

AbstractUndoped polysilicon layers deposited at 620 °C onto a silicon wafer induce a compressive stress of approximately 1 × 109 dynes/cm2 resulting in a bow of the wafer. This stress can be relieved by rapid annealing at temperatures above 1000 °C. A comparison with conventional furnace annealing reveals that the stress relaxation is a weak function of time and strongly depends on temperature. Rapid thermal processing also causes immediate rearrangement of the film structure, as observed by X-ray diffraction. Although both stress and film texture change with annealing, no conclusive relationship is observed.

1987 ◽  
Vol 92 ◽  
Author(s):  
A. Usami ◽  
Y. Tokuda ◽  
H. Shiraki ◽  
H. Ueda ◽  
T. Wada ◽  
...  

ABSTRACTRapid thermal processing using halogen lamps was applied to the diffusion of Zn into GaAs0.6 P0.4:Te from Zn-doped oxide films. The Zn diffusion coefficient of the rapid thermal diffused (RTD) samples at 800°C for 6 s was about two orders of magnitude higher than that of the conventional furnace diffused samples at 800°C for 60 min. The enhanced diffusion of Zn by RTD may be ascribed to the stress field due to the difference in the thermal expansion coefficient between the doped oxide films and GaAs0.6P0.4 materials, and due to the temperature gradient in GaAs0.6P0 4 materials. The Zn diffusion coefficient at Zn concentration of 1.0 × l018 cm−3 was 3.6 × 10−11, 3.1 × 10−11 and 5.0 × 10−12 cm2 /s for the RTD samples at 950°C for 6 s from Zn-, (Zn,Ga)- and (Zn,P)-doped oxide films, respectively. This suggests that Zn diffusibility was controlled by the P in the doped oxide films.


1997 ◽  
Vol 485 ◽  
Author(s):  
Chih-hung Chang ◽  
Billy Stanbery ◽  
Augusto Morrone ◽  
Albert Davydov ◽  
Tim Anderson

AbstractCuInSe2 thin films have been synthesized from binary precursors by Rapid Thermal Processing (RTP) at a set-point temperature of 290°C for 70 s. With appropriate processing conditions no detrimental Cu2-xSe phase was detected in the CIS films. The novel binary precursor approach consisted of a bilayer structure of In-Se and Cu-Se compounds. This bilayer structure was deposited by migration enhanced physical vapor deposition at a low temperature (200°C) and the influence of deposition parameters on the precursor film composition was determined. The bilayer structure was then processed by RTP and characterized for constitution by X-ray diffraction and for composition by Wavelength Dispersive X-ray Spectroscopy.


1987 ◽  
Vol 92 ◽  
Author(s):  
E. Ma ◽  
M. Natan ◽  
B.S. Lim ◽  
M-A. Nicolet

ABSTRACTSilicide formation induced by rapid thermal annealing (RTA) and conventional furnace annealing (CFA) in bilayers of sequentially deposited films of amorphous silicon and polycrystalline Co or Ni is studied with RBS, X-ray diffraction and TEM. Particular attention is paid to the reliability of the RTA temperature measurements in the study of the growth kinetics of the first interfacial compound, Co2Si and Ni2Si, for both RTA and CFA. It is found that the same diffusion-controlled kinetics applies for the silicide formation by RTA in argon and CFA in vacuum with a common activation energy of 2.1+0.2eV for Co2Si and 1.3+0.2eV for Ni Si. Co and Ni atoms are the dominant diffusing species; during silicide formation by both RTA and CFA. The microstructures of the Ni-silicide formed by the two annealing techniques, however, differs considerably from each other, as revealed by cross-sectional TEM studies.


1993 ◽  
Vol 303 ◽  
Author(s):  
R.P.S. Thakur ◽  
A. Martin ◽  
W.T. Fackrell ◽  
R. Barbour ◽  
J. L. Kawski ◽  
...  

ABSTRACTSingle wafer rapid thermal processing (RTP) is emerging as a key player in the processing of advanced sub-half micron memory devices. The high temperature processing of large diameter silicon wafers can create sufficient thermal stress for generation of dislocation, slip, and gross mechanical instability of the wafer. The aforementioned factors may lead to loss of device yield, dielectric defects, and reduced photolithographic yield due to degradation of virtual wafer flatness. Moreover, the loss of geometrical planarity of wafer due to warpage can make it impossible to process a wafer or can lead to self-fracture of the wafer.In this paper we present the warpage and stress results of our study on plain and patterned structures that were subjected to RTP at different stages of the CMOS process flow. Experimental results have been gathered with full wafer scanning technology using non-contact capacitive probes to measure more accurate global stress values. The stress and warpage values on the patterned wafers could be measured accurately without any light scattering effects and destructive interference. It is reported that the thermal processing creates significant variations in shape change around the wafer which could be identified using the full wafer data set acquired using this evaluation technique. We have successfully tracked variations in film stress for both plain and patterned structures as a cumulative effect and correlated it with the overall wafer warpage. The effects of incoming wafer warpage, ramp rate in RTP, and high stress nitride films on the overall wafer warpage are also reported.


2013 ◽  
Vol 644 ◽  
pp. 161-164
Author(s):  
Wu Tang ◽  
Ji Jun Yang ◽  
Chi Ming Li

In this paper, Al2O3 thin film samples were deposited on Si-(100) substrate by electron beam evaporation with different thickness at substrate temperature 400°C and after that, annealed in the air at 500°C with different time. The structure, thickness and residual stress of these films were measured by X-ray diffraction (XRD), stylus profiler and electronic thin film stress distribution tester, respectively. The effects of several parameters on the properties of Al2O3 films were studied. In addition, the relations between thickness and residual stress of Al2O3 thin films as the high-k gate dielectric was analyzed. The results shown that the residual stress becomes smaller after annealing, the residual stress was depressed down to maximum value 300MPa from 580MPa for annealing time 30min, and depressed down to minimum value 220MPa from 580MPa for annealing time 60min. But eventually, it has a critical film thickness point on the scale.


2015 ◽  
Vol 86 (1) ◽  
pp. 013902 ◽  
Author(s):  
Md. Imteyaz Ahmad ◽  
Douglas G. Van Campen ◽  
Jeremy D. Fields ◽  
Jiafan Yu ◽  
Vanessa L. Pool ◽  
...  

1988 ◽  
Vol 126 ◽  
Author(s):  
Yutaka Tokuda ◽  
Masayuki Katayama ◽  
Nobuo Ando ◽  
Akio Kitagawa ◽  
Akira Usami ◽  
...  

ABSTRACTEffects of rapid thermal processing (RTP) on SiO2/GaAs interfaces have been investigated with Auger electron spectroscopy and X-ray photoelectron spectroscopy. SiO2 films of 100, 175, 200 and 1250 nm thickness have been deposited on liquid encapsulated Czochralski-grown (100) n-type GaAs wafers by the RF sputtering method. RTP has been performed at 800°C for 6 s. For comparison, conventional furnace processing (CFP) has also been performed at 800°C for 20 min for 200-nm-thick SiO2/GaAs. The Ga is observed on the outer SiO2 surface for RTP samples as well as CFP samples. This indicates that the outdiffusion of Ga occurs after only 6 s at 800°C even through 1250-nm-thick SiO2 films. The depth profile of Ga reveals the pile-up of Ga on the outer SiO2 surface for both RTP and CFP samples. The amount of Ga on the outer surface gradually increases in the thickness range 1250 to 175 nm. The As is also observed on the outer surface. The amount of Ga and As on the outer surface rapidly increases at 100 nm thickness. Electron traps in RTP samples have been studied with deep-level transient spectroscopy. Different electron traps are produced in GaAs by RTP between 100-nm- and 200-nm-thick SiO2/GaAs. It is thought that the production of different traps by RTP is related to the amount of Ga and As loss through SiO2 films from GaAs.


1993 ◽  
Vol 303 ◽  
Author(s):  
Peter Y. Wong ◽  
Christopher K. Hess ◽  
Ioannis N. Miaoulis

ABSTRACTThe individual film thicknesses of multilayered structures processed by rapid thermal processing are of the same order as the wavelengths of the incident radiation. This induces optical interference effects which are responsible for the strong dependency of surface reflectivity, emissivity, and temperature distributions on the geometry of the layering structures, presence of patterns, and thickness of the films. A two-dimensional, finitedifference numerical model has been developed to investigate this microscale radiation phenomena and identify the critical processing parameters which affect rapid thermal processing of multilayer thin films. The uniformity of temperature distributions throughout the wafer during rapid thermal processing is directly affected by incident heater configurations, ramping conditions, wafer-edge effects, and thin-film layering structure. Results from the numerical model for various film structures are presented for chemical vapor deposition of polycrystalline silicon over oxide films on substrate. A novel technique using an edge-enhanced wafer which has a different film structure near its edge is presented as a control over the transient temperature distribution.


1998 ◽  
Vol 525 ◽  
Author(s):  
A. R. Abramson ◽  
H. Tadal ◽  
P. Nieva ◽  
P. Zavracky ◽  
I. N. Miaoulis ◽  
...  

ABSTRACTThe radiative properties of a silicon wafer undergoing Rapid Thermal Processing (RTP) are contingent upon the doping level of the silicon substrate and film structure on the wafer, and fluctuate drastically with temperature and wavelength. For a lightly doped substrate, partial transparency effects must be considered that significantly affect absorption characteristics. Band gap, free carrier, and lattice absorption are the dominant absorption mechanisms and either individually or in concert have considerable effect on the overall absorption coefficient of the silicon wafer. At high doping levels, partial transparency effects dissipate, and the substrate may be considered optically thick. A numerical model has been developed to examine partial transparency effects, and to compare lightly doped (partially transparent) and heavily doped (opaque) silicon wafers with a multilayer film structure during RTP.


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