Nitridation of vanadium in molecular nitrogen: a comparison of rapid thermal processing (RTP) and conventional furnace annealing

AbstractUndoped polysilicon layers deposited at 620 °C onto a silicon wafer induce a compressive stress of approximately 1 × 109 dynes/cm2 resulting in a bow of the wafer. This stress can be relieved by rapid annealing at temperatures above 1000 °C. A comparison with conventional furnace annealing reveals that the stress relaxation is a weak function of time and strongly depends on temperature. Rapid thermal processing also causes immediate rearrangement of the film structure, as observed by X-ray diffraction. Although both stress and film texture change with annealing, no conclusive relationship is observed.

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Diffusion of Zn into Gaas 0.6 P0.4:Te From Zn-Doped Oxide Films By Rapid Thermal Processing

MRS Proceedings ◽

10.1557/proc-92-393 ◽

1987 ◽

Vol 92 ◽

Cited By ~ 6

Author(s):

A. Usami ◽

Y. Tokuda ◽

H. Shiraki ◽

H. Ueda ◽

T. Wada ◽

...

Keyword(s):

Diffusion Coefficient ◽

Thermal Processing ◽

Rapid Thermal Processing ◽

Oxide Films ◽

Zn Diffusion ◽

Enhanced Diffusion ◽

Conventional Furnace ◽

Zn Concentration ◽

The Difference ◽

Doped Oxide

ABSTRACTRapid thermal processing using halogen lamps was applied to the diffusion of Zn into GaAs0.6 P0.4:Te from Zn-doped oxide films. The Zn diffusion coefficient of the rapid thermal diffused (RTD) samples at 800°C for 6 s was about two orders of magnitude higher than that of the conventional furnace diffused samples at 800°C for 60 min. The enhanced diffusion of Zn by RTD may be ascribed to the stress field due to the difference in the thermal expansion coefficient between the doped oxide films and GaAs0.6P0.4 materials, and due to the temperature gradient in GaAs0.6P0 4 materials. The Zn diffusion coefficient at Zn concentration of 1.0 × l018 cm−3 was 3.6 × 10−11, 3.1 × 10−11 and 5.0 × 10−12 cm2 /s for the RTD samples at 950°C for 6 s from Zn-, (Zn,Ga)- and (Zn,P)-doped oxide films, respectively. This suggests that Zn diffusibility was controlled by the P in the doped oxide films.

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omparisons of Silicide Formation by Rapid Thermal Annealing and Conventional Furnace Annealing

MRS Proceedings ◽

10.1557/proc-92-205 ◽

1987 ◽

Vol 92 ◽

Cited By ~ 2

Author(s):

E. Ma ◽

M. Natan ◽

B.S. Lim ◽

M-A. Nicolet

Keyword(s):

Thermal Annealing ◽

Rapid Thermal Annealing ◽

Silicide Formation ◽

X Ray Diffraction ◽

Furnace Annealing ◽

Cross Sectional ◽

Conventional Furnace ◽

Diffusion Controlled ◽

Conventional Furnace Annealing ◽

Kinetics Of

ABSTRACTSilicide formation induced by rapid thermal annealing (RTA) and conventional furnace annealing (CFA) in bilayers of sequentially deposited films of amorphous silicon and polycrystalline Co or Ni is studied with RBS, X-ray diffraction and TEM. Particular attention is paid to the reliability of the RTA temperature measurements in the study of the growth kinetics of the first interfacial compound, Co2Si and Ni2Si, for both RTA and CFA. It is found that the same diffusion-controlled kinetics applies for the silicide formation by RTA in argon and CFA in vacuum with a common activation energy of 2.1+0.2eV for Co2Si and 1.3+0.2eV for Ni Si. Co and Ni atoms are the dominant diffusing species; during silicide formation by both RTA and CFA. The microstructures of the Ni-silicide formed by the two annealing techniques, however, differs considerably from each other, as revealed by cross-sectional TEM studies.

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Rapid Optical Annealing for Improved GaAs Fet Uniformity

MRS Proceedings ◽

10.1557/proc-52-397 ◽

1985 ◽

Vol 52 ◽

Cited By ~ 2

Author(s):

Thomas E. Kazior ◽

Kamal Tabatabaie-Alavi

Keyword(s):

Low Noise ◽

Drift Mobility ◽

Gate Length ◽

Furnace Annealing ◽

Zero Bias ◽

Conventional Furnace ◽

Conventional Furnace Annealing ◽

Performance Results ◽

Doping Profiles ◽

Excellent Reproducibility

ABSTRACTAn Eaton Nova Rapid Optical Annealer (ROA 400) has been used to activate n and n+ Si implants for use in power and low noise FET structures for GaAs MMIC's. PECVD SiN capped 3" SI GaAs wafers were annealed at temperatures ranging from 800 to 970 °C for times ranging from 0 (transient light pulse) to 20 sec. Doping profiles were determined using a Polaron concentration profiler; FATFET's were used for measuring drift mobility; and short gate (l.0μm gate length) FET's were fabricated to establish activation uniformity and to determine d.c. and r.f. performance. Results have indicated peak implant activation as high as 90% and electron mobilities of up to 4700cm2/V-sec for carrier concentrations of 1.3×1017/cm3 – results comparable to conventional furnace annealing. The most significant improvement of optical annealing comes in device uniformity. Saturated current uniformities of < ±3% have been achieved over 3" wafers with excellent reproducibility from wafer to wafer. Power FET structures with zero bias gm of 120mS/mm with uniformities of <±5mS/mm have been measured. R.f. measurements on these devices yielded output powers of >500mW/mm with power added efficiencies as high as 35%.

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A New Annealing Method to Obtain High Quality Poly-Si

MRS Proceedings ◽

10.1557/proc-283-745 ◽

1992 ◽

Vol 283 ◽

Author(s):

Yoon-Ho Song ◽

Jong-Tae Baek ◽

Kee-Soo Nam ◽

Sang-Won Kang

Keyword(s):

Field Effect ◽

Field Effect Mobility ◽

High Quality ◽

Furnace Annealing ◽

Conventional Furnace ◽

Good Uniformity ◽

Conventional Furnace Annealing ◽

Annealing Method ◽

Si Thin Film ◽

Free Nucleus

ABSTRACTA new annealing method, a combination of rapid thermal annealing (RTA) and furnace annealing, has been developed to obtain a high quality poly-Si from a-Si deposited by LPCVD. This method produces a large grain poly-Si with good uniformity, which may result from the growth of relatively defect-free nucleus generated at a high temperature by RTA. Poly-Si thin film transistors fabricated by this new annealing method have higher field effect mobility and better uniformity compared with those by the conventional furnace annealing.

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Quantum State in Solid-Phase Crystallization of a-Si:H by FA

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.44-47.4154 ◽

2010 ◽

Vol 44-47 ◽

pp. 4154-4156

Author(s):

Rui Min Jin ◽

Ding Zhen Li ◽

Lan Li Chen ◽

Xiang Ju Han ◽

Jing Xiao Lu

Keyword(s):

Thin Film ◽

Annealing Temperature ◽

Solid Phase ◽

Quantum States ◽

Solid Phase Crystallization ◽

Furnace Annealing ◽

Conventional Furnace ◽

Different Temperatures ◽

Conventional Furnace Annealing ◽

Electronic Microscope

Amorphous silicon films prepared by PECVD on glass substrate has been crystallized by conventional furnace annealing (FA) at different temperatures. From the Raman spectra and scanning electronic microscope (SEM), it is found that the thin film grain size present quantum states with annealing temperature.

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Effects of Rapid Thermal Processing on SiO2/GaAs Interfaces

MRS Proceedings ◽

10.1557/proc-126-215 ◽

1988 ◽

Vol 126 ◽

Cited By ~ 1

Author(s):

Yutaka Tokuda ◽

Masayuki Katayama ◽

Nobuo Ando ◽

Akio Kitagawa ◽

Akira Usami ◽

...

Keyword(s):

Outer Surface ◽

Photoelectron Spectroscopy ◽

Thermal Processing ◽

Deep Level ◽

Rapid Thermal Processing ◽

Rf Sputtering ◽

Electron Traps ◽

Conventional Furnace ◽

Pile Up ◽

Transient Spectroscopy

ABSTRACTEffects of rapid thermal processing (RTP) on SiO2/GaAs interfaces have been investigated with Auger electron spectroscopy and X-ray photoelectron spectroscopy. SiO2 films of 100, 175, 200 and 1250 nm thickness have been deposited on liquid encapsulated Czochralski-grown (100) n-type GaAs wafers by the RF sputtering method. RTP has been performed at 800°C for 6 s. For comparison, conventional furnace processing (CFP) has also been performed at 800°C for 20 min for 200-nm-thick SiO2/GaAs. The Ga is observed on the outer SiO2 surface for RTP samples as well as CFP samples. This indicates that the outdiffusion of Ga occurs after only 6 s at 800°C even through 1250-nm-thick SiO2 films. The depth profile of Ga reveals the pile-up of Ga on the outer SiO2 surface for both RTP and CFP samples. The amount of Ga on the outer surface gradually increases in the thickness range 1250 to 175 nm. The As is also observed on the outer surface. The amount of Ga and As on the outer surface rapidly increases at 100 nm thickness. Electron traps in RTP samples have been studied with deep-level transient spectroscopy. Different electron traps are produced in GaAs by RTP between 100-nm- and 200-nm-thick SiO2/GaAs. It is thought that the production of different traps by RTP is related to the amount of Ga and As loss through SiO2 films from GaAs.

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Shallow Silicided Junctions for VLSI Cmos Transistors by Furnace and Rapid Thermal Processing

MRS Proceedings ◽

10.1557/proc-71-417 ◽

1986 ◽

Vol 71 ◽

Cited By ~ 3

Author(s):

A.L. Butler ◽

D.J. Foster ◽

A.J. Pickering

Keyword(s):

Thermal Processing ◽

Rapid Thermal Processing ◽

Device Performance ◽

Optimum Conditions ◽

Furnace Annealing ◽

Boron Fluoride ◽

Device Scaling ◽

Diffusion Effects ◽

Silicon Implantation ◽

Better Than

AbstractAs a result of device scaling very shallow low resistance diffusions are required for VLSI CMOS fabrication. This paper describes a technique for their formation using silicon implantation for preamorphisation, counterdoping arsenic implantation and overall boron fluoride implantation for the sources and drains of the n- and p-channel transistors. Platinum silicidation has been used to reduce diffusion and polysilicon sheet resistances to 8Q/square. Activation of the shallow diffusions has been achieved either by furnace annealing (FA) or rapid thermal annealing (RTA) in the range 900°C to 1100 °C. Materials results are discussed including TTEM, SIMS and SR profiling. The suitability of the technique for VLSI CMOS applications is demonstrated by the fabrication of sub-micron transistors. With larger wafer diameters (>5') the FA conditions considered are not practicable owing to ramped diffusion effects which lead to deeper junctions. Hence RTA is necessary: optimum conditions found were 1100 °C for 10 seconds when device performance equivalent to or better than FA can be achieved.

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Smooth Silicide Formation by Ion Beam Mixing of Ti/Si-Layers

MRS Proceedings ◽

10.1557/proc-74-443 ◽

1986 ◽

Vol 74 ◽

Cited By ~ 1

Author(s):

K. Kohlhof ◽

S. Mantl ◽

B. Stritzker

Keyword(s):

Ion Beam ◽

Liquid Nitrogen Temperature ◽

Silicide Formation ◽

Furnace Annealing ◽

Ion Beam Mixing ◽

X Ray ◽

Surfaces And Interfaces ◽

Conventional Furnace ◽

Conventional Furnace Annealing ◽

Substrate Temperatures

AbstractIon beam mixing experiments of Ti-Si layers have been performed with Kr ions of 250 keV energy and doses ranging from 7 1015 to 7 1016 cm-2 at temperatures between liquid nitrogen temperature and 450°C. At substrate temperatures below 120°C no silicide formation could be detected. Only weak mixing at the Ti-Si interface is observed. At temperatures above 120°C the formation of TiSi2 could be verified by Rutherford backscattering and X-ray diffractometry. Layers of TiSi2 produced by ion beam mixing show smooth surfaces in contrast to those prepared by conventional furnace annealing. Those display rough surfaces and interfaces.

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