Reliability Implications of Defects in High Temperature Annealed Si/SiO2/Si Structures

1994 ◽  
Vol 338 ◽  
Author(s):  
W. L. Warren ◽  
D. M. Fleetwood ◽  
M. R. Shaneyfelt ◽  
P. S. Winokur ◽  
R. A. B. Devine ◽  
...  
Keyword(s):  
High Temperature ◽  
Chemical Potential ◽  
Field Effect Transistors ◽  
Radiation Sensitivity ◽  
Oxide Semiconductor ◽  
Interfacial Region ◽  
Si Substrate ◽  
Paramagnetic Defect ◽  
Chemical Potential Difference ◽  
Hole Trapping

ABSTRACTHigh-temperature post-oxidation annealing of poly-Si/SiO2/Si structures such as metal-oxidesemiconductor capacitors and metal-oxide-semiconductor field effect transistors is known to result in enhanced radiation sensitivity, increased 1/f noise, and low field breakdown. We have studied the origins of these effects from a spectroscopic standpoint using electron paramagnetic resonance (EPR) and atomic force microscopy. One result of high temperature annealing is the generation of three types of paramagnetic defect centers, two of which are associated with the oxide close to the Si/SiO2 interface (oxygen-vacancy centers) and the third with the bulk Si substrate (oxygen-related donors). In all three cases the origin of the defects may be attributed to out-diffusion of O from the SiO2 network into the Si substrate with associated reduction of the oxide. We present a straightforward model for the interfacial region which assumes the driving force for O out-diffusion is the chemical potential difference of the O in the two phases (SiO2 and the Si substrate). Experimental evidence is provided to show that enhanced hole trapping and interface-trap and border-trap generation in irradiated high-temperature annealed Si/SiO2/Si systems are all related either directly, or indirectly, to the presence of oxygen vacancies.

High-temperature modeling and characterization of 6H silicon carbide metal-oxide-semiconductor field-effect transistors

2005 ◽  
Vol 97 (4) ◽  
pp. 046106 ◽  
Author(s):  
Stephen K. Powell ◽  
Neil Goldsman ◽  
Aivars Lelis ◽  
James M. McGarrity ◽  
Flynn B. McLean
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Temperature Modeling

Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Synthesis ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Timing Models ◽  
High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

Hole Trapping in the NBTI Characteristic of SiC MOSFETs

2018 ◽  
Vol 924 ◽  
pp. 667-670
Author(s):  
Yan Jing He ◽  
Hong Liang Lv ◽  
Xiao Yan Tang ◽  
Qing Wen Song ◽  
Yi Meng Zhang ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Threshold Voltage Shift ◽  
Hole Trapping ◽  
Primary Mechanism ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
P Type

P-type implanted metal oxide semiconductor capacitors (MOSCAPs) and metal oxide semiconductor field effect transistors (MOSFETs) have been fabricated. The characteristics of hole trapping at the interface of SiO2/SiC are investigated through capacitance-voltage (CV) measurements with different starting voltages. The negative shift voltage ∆Vshift and the hysteresis voltages ∆VH which caused by the hole traps in the MOSCAPs and MOSFETs are extracted from CV results. The results show that the hole traps extracted from MOSCAPs are larger than the that extracted from the threshold voltage shift in the MOSFETs. It suggests holes trapping are the primary mechanism contributing to the NBTI, but not all the holes work. Part of the hole traps are compensation by sufficient electrons in the MOSFET structure.

Improved Characteristics of SiC MOSFETs by Post-Oxidation Annealing in Ar at High Temperature

2011 ◽  
Vol 679-680 ◽  
pp. 445-448 ◽  
Author(s):  
Muneharu Kato ◽  
Yuichiro Nanen ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
High Temperature ◽  
Thermal Oxidation ◽  
Field Effect ◽  
Secondary Ion Mass Spectrometry ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Gate Oxides ◽  
Secondary Ion ◽  
Improved Characteristics ◽  
Peak Value

Post-oxidation annealing (POA) in Ar at high temperature has been performed during fabrication of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The gate oxides were formed by thermal oxidation followed by N2O annealing, then annealed in Ar for 30 min or 5 h at 1300 °C. The results of Secondary Ion Mass Spectrometry (SIMS) measurements indicated that the C atoms accumulated at the SiO2/SiC interface by thermal oxidation diffused during the 5h-Ar annealing. The characteristics of n-channel MOSFETs were improved and the peak value of field effect mobility was increased to 33 cm2/Vs from 19 cm2/Vs by extending the Ar annealing time.

Silicon Carbide Power Field-Effect Transistors

MRS Bulletin ◽  
2005 ◽  
Vol 30 (4) ◽  
pp. 293-298 ◽  
Author(s):  
Jian H. Zhao
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Field Effect ◽  
Recent Progress ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
High Power Density ◽  
Advantages And Disadvantages ◽  
Power Switches

AbstractSilicon carbide power field-effect transistors, including power vertical-junction FETs (VJFETs) and metal oxide semiconductor FETs (MOSFETs), are unipolar power switches that have been investigated for high-temperature and high-power-density applications. Recent progress and results will be reviewed for different device designs such as normally-OFF and normally-ON VJFETs, double-implanted MOSFETs, and U-shaped-channel MOSFETs. The advantages and disadvantages of SiC VJFETs and MOSFETs will be discussed. Remaining challenges will be identified.

TDDB Lifetime Enhancement in SiC-MOSFETs under Gate-Switching Pperation

2020 ◽  
Vol 1004 ◽  
pp. 665-670
Author(s):  
Eiichi Murakami ◽  
Tatsuya Takeshita ◽  
Kazuhiro Oda
Keyword(s):  
Dielectric Breakdown ◽  
Defect Density ◽  
Field Effect Transistors ◽  
Stress Test ◽  
Anomalous Behavior ◽  
Oxide Semiconductor ◽  
Continuous Increase ◽  
Hole Trapping ◽  
The Impact ◽  
Lifetime Enhancement

Gate oxide integrity (GOI) are the most important concern in automotive applications of SiC-metal-oxide-semiconductor field-effect transistors (MOSFETs). As well as for the so-called B-mode defect density reduction, the time-dependent dielectric breakdown (TDDB) mechanism including the B-mode should be clarified in comparison to Si-MOSFETs. We have reported an anomalous behavior in the form of a continuous increase in the gate current during a Fowler-Nordheim stress test of commercially available SiC-MOSFETs, which we attributed to hole trapping near the SiO2/SiC interface. In this paper, the impact of this phenomenon on the TDDB lifetime is investigated, and the effects of AC on the TDDB lifetime enhancement in SiC-MOSFET under gate-switching operations (1 kHz and 100 kHz, at room temperature) are reported.

Properties of a Lattice Gas Model for 3He–4He Mixtures II: Analysis of High Temperature Series for the f.c.c. Lattice

1975 ◽  
Vol 53 (10) ◽  
pp. 987-1002 ◽  
Author(s):  
M. Plischke ◽  
D. D. Betts
Keyword(s):  
High Temperature ◽  
Specific Heat ◽  
Lattice Gas ◽  
Chemical Potential ◽  
Constant Pressure ◽  
Temperature Series ◽  
Adjustable Parameter ◽  
Constant Density ◽  
Constant Concentration ◽  
Chemical Potential Difference

For the Cheng–Schick model of 3He–4He mixtures high temperature series expansions at (a) constant density and constant concentration and (b) constant pressure and constant chemical potential difference are presented for the f.c.c. lattice for the fluctuation in the superfluid order parameter, the concentration susceptibility, and the specific heat at constant chemical potential. Analysis of the fluctuation series yields well defined lambda temperatures. In addition analysis of the concentration susceptibility series provides a less precise estimate of the tricritical concentration. The specific heat series have not proved very amenable to analysis. Upon fixing a single adjustable parameter the lambda curve of the model agrees precisely with experiment for all 3He concentrations. Estimates of tricritical exponents could not be obtained.

scholarly journals Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

2019 ◽  
Vol 14 (2) ◽  
pp. 1-8
Author(s):  
Egon Henrique Salerno Galembeck ◽  
Denis Flandre ◽  
Christian Renaux ◽  
Salvador Pinillos Gimenez
Keyword(s):  
High Temperature ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Soi Mosfet ◽  
Temperature Conditions ◽  
Channel Lengths

This present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions.  To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.

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