TDDB Lifetime Enhancement in SiC-MOSFETs under Gate-Switching Pperation

2020 ◽  
Vol 1004 ◽  
pp. 665-670
Author(s):  
Eiichi Murakami ◽  
Tatsuya Takeshita ◽  
Kazuhiro Oda
Keyword(s):  
Dielectric Breakdown ◽  
Defect Density ◽  
Field Effect Transistors ◽  
Stress Test ◽  
Anomalous Behavior ◽  
Oxide Semiconductor ◽  
Continuous Increase ◽  
Hole Trapping ◽  
The Impact ◽  
Lifetime Enhancement

Gate oxide integrity (GOI) are the most important concern in automotive applications of SiC-metal-oxide-semiconductor field-effect transistors (MOSFETs). As well as for the so-called B-mode defect density reduction, the time-dependent dielectric breakdown (TDDB) mechanism including the B-mode should be clarified in comparison to Si-MOSFETs. We have reported an anomalous behavior in the form of a continuous increase in the gate current during a Fowler-Nordheim stress test of commercially available SiC-MOSFETs, which we attributed to hole trapping near the SiO2/SiC interface. In this paper, the impact of this phenomenon on the TDDB lifetime is investigated, and the effects of AC on the TDDB lifetime enhancement in SiC-MOSFET under gate-switching operations (1 kHz and 100 kHz, at room temperature) are reported.

Reliability Implications of Defects in High Temperature Annealed Si/SiO2/Si Structures

1994 ◽  
Vol 338 ◽  
Author(s):  
W. L. Warren ◽  
D. M. Fleetwood ◽  
M. R. Shaneyfelt ◽  
P. S. Winokur ◽  
R. A. B. Devine ◽  
...  
Keyword(s):  
High Temperature ◽  
Chemical Potential ◽  
Field Effect Transistors ◽  
Radiation Sensitivity ◽  
Oxide Semiconductor ◽  
Interfacial Region ◽  
Si Substrate ◽  
Paramagnetic Defect ◽  
Chemical Potential Difference ◽  
Hole Trapping

ABSTRACTHigh-temperature post-oxidation annealing of poly-Si/SiO2/Si structures such as metal-oxidesemiconductor capacitors and metal-oxide-semiconductor field effect transistors is known to result in enhanced radiation sensitivity, increased 1/f noise, and low field breakdown. We have studied the origins of these effects from a spectroscopic standpoint using electron paramagnetic resonance (EPR) and atomic force microscopy. One result of high temperature annealing is the generation of three types of paramagnetic defect centers, two of which are associated with the oxide close to the Si/SiO2 interface (oxygen-vacancy centers) and the third with the bulk Si substrate (oxygen-related donors). In all three cases the origin of the defects may be attributed to out-diffusion of O from the SiO2 network into the Si substrate with associated reduction of the oxide. We present a straightforward model for the interfacial region which assumes the driving force for O out-diffusion is the chemical potential difference of the O in the two phases (SiO2 and the Si substrate). Experimental evidence is provided to show that enhanced hole trapping and interface-trap and border-trap generation in irradiated high-temperature annealed Si/SiO2/Si systems are all related either directly, or indirectly, to the presence of oxygen vacancies.

Insight into Channel Conduction Mechanisms of 4H-SiC(0001) MOSFET Based on Temperature-Dependent Hall Effect Measurement

2020 ◽  
Vol 1004 ◽  
pp. 620-626
Author(s):  
Hironori Takeda ◽  
Mitsuru Sometani ◽  
Takuji Hosoi ◽  
Takayoshi Shimura ◽  
Hiroshi Yano ◽  
...  
Keyword(s):  
Hall Effect ◽  
Field Effect ◽  
Elevated Temperatures ◽  
Field Effect Transistors ◽  
Free Carrier ◽  
Oxide Semiconductor ◽  
Thermal Excitation ◽  
Temperature Dependent ◽  
Conduction Mechanisms ◽  
The Impact

Temperature-dependent Hall effect measurements were conducted to investigate the channel conduction mechanisms of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). This method allows us to discriminate the impact of the density of mobile (free) carriers in the inversion channels and their net mobility on the performance of SiC MOSFETs. It was found that, while the free carrier ratio of SiC MOSFETs with conventional gate oxides formed by dry oxidation is below 4% at 300 K, increasing the free carrier ratio due to thermal excitation of trapped electrons from SiO2/SiC interfaces leads to an unusual improvement in the field-effect mobility of SiC MOSFETs at elevated temperatures. Specifically, a significant increase in free carrier density surpasses the mobility degradation caused by phonon scattering for thermally grown SiO2/SiC interfaces. It was also found that, although nitrogen incorporation in SiO2/SiC interfaces increases the free carrier ratio typically up to around 30%, introduction of an additional scattering factor associated with interface nitridation compensates for the moderate amount of thermally generated mobile carriers at high temperatures, indicating a fundamental drawback of nitridation of SiO2/SiC interfaces. On the basis of these findings, we discuss the channel conduction mechanisms of SiC MOSFETs.

Fabrication of MISFET exhibiting normally-off characteristics using a single-crystalline InGaO3(ZnO)5 thin film

2002 ◽  
Vol 747 ◽  
Author(s):  
K. Nomura ◽  
H. Ohta ◽  
K. Ueda ◽  
T. Kamiya ◽  
M. Hirano ◽  
...  
Keyword(s):  
Thin Film ◽  
Field Effect ◽  
Defect Density ◽  
Field Effect Transistors ◽  
Solid Phase ◽  
Oxide Semiconductor ◽  
Single Crystalline ◽  
Transparent Oxide ◽  
Improved Performance ◽  
Transparent Oxide Semiconductors

ABSTRACTTransparent metal-insulator-semiconductor field-effect transistors (MISFETs) were fabricated using a single-crystalline thin film of an n-type transparent oxide semiconductor, a homologous compound InGaO3(ZnO)5, grown by a reactive solid phase epitaxy method. The transparent MISFET exhibited good performances with “normally-off characteristics”, “an on/off current ratio as large as 105” and “insensitivity to visible light”. Field-effect mobility was about 2 cm2(Vs)-1, which is larger than those reported previously for MISFETs fabricated in transparent oxide semiconductors. These improved performance is thought to result from the low defect density and intrinsic-level carrier concentration of the single-crystalline InGaO3(ZnO)5 film.

Hole Trapping in the NBTI Characteristic of SiC MOSFETs

2018 ◽  
Vol 924 ◽  
pp. 667-670
Author(s):  
Yan Jing He ◽  
Hong Liang Lv ◽  
Xiao Yan Tang ◽  
Qing Wen Song ◽  
Yi Meng Zhang ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Threshold Voltage Shift ◽  
Hole Trapping ◽  
Primary Mechanism ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
P Type

P-type implanted metal oxide semiconductor capacitors (MOSCAPs) and metal oxide semiconductor field effect transistors (MOSFETs) have been fabricated. The characteristics of hole trapping at the interface of SiO2/SiC are investigated through capacitance-voltage (CV) measurements with different starting voltages. The negative shift voltage ∆Vshift and the hysteresis voltages ∆VH which caused by the hole traps in the MOSCAPs and MOSFETs are extracted from CV results. The results show that the hole traps extracted from MOSCAPs are larger than the that extracted from the threshold voltage shift in the MOSFETs. It suggests holes trapping are the primary mechanism contributing to the NBTI, but not all the holes work. Part of the hole traps are compensation by sufficient electrons in the MOSFET structure.

1.4kV Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2011 ◽  
Vol 679-680 ◽  
pp. 607-612 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Kazuto Takao ◽  
Masaru Furukawa ◽  
Makoto Mizukami ◽  
...  
Keyword(s):  
Room Temperature ◽  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Mos Capacitor ◽  
Time Dependent Dielectric Breakdown ◽  
Blocking Voltage ◽  
Switching Characteristics

1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.

Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures

2014 ◽  
Vol 778-780 ◽  
pp. 595-598 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Breakdown Field ◽  
Static Capacitance ◽  
Capacitance Voltage ◽  
Oxide Deposition ◽  
Mos Structures ◽  
Field Strengths

This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.

Sign in / Sign up

Export Citation Format

Share Document