Temperature and Doping Dependency of Piezoresistivity in p-type Silicon

ABSTRACTWe have performed new measurements of the temperature and doping dependency of the piezoresistive effect in p-type silicon. Piezoresistivity is one of the most common sensing principles of micro-electro-mechanical-systems (MEMS). Our measurements are performed in a specially designed setup based on the well-known 4 point bending technique. The samples are beams of full wafer thickness. To minimize leakage currents and to obtain uniform doping profiles, we have used SIMOX (Separation by IMplantation of OXygen) substrates with resistors defined in an epitaxial layer. Spreading resistance measurements show that the doping profiles are uniform with depth, while measurements of leakage current versus temperature indicate low leakage current. In this paper we present results for the doping concentration range from 1×1017 – 1×1020 cm−3 and the temperature range from –30 to 150 degrees Celsius. The results show a doping dependency of piezoresistivity well described by the current models. The measurements of the temperature dependency of the coefficients of piezoresistivity are compared to a linear model with a negative temperature coefficient whose absolute value decreases with increasing doping.

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Low-Leakage-Current Enhancement-Mode AlGaN/GaN Heterostructure Field-Effect Transistor Using p-Type Gate Contact

Japanese Journal of Applied Physics ◽

10.1143/jjap.45.l319 ◽

2006 ◽

Vol 45 (No. 11) ◽

pp. L319-L321 ◽

Cited By ~ 26

Author(s):

Norio Tsuyukuchi ◽

Kentaro Nagamatsu ◽

Yoshikazu Hirose ◽

Motoaki Iwaya ◽

Satoshi Kamiyama ◽

...

Keyword(s):

Leakage Current ◽

Field Effect ◽

Field Effect Transistor ◽

Enhancement Mode ◽

Low Leakage ◽

Low Leakage Current ◽

Effect Transistor ◽

Gan Heterostructure ◽

P Type

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New High-Voltage Unipolar Mode p+ Si/n– 4H-SiC Heterojunction Diode

Materials Science Forum ◽

10.4028/www.scientific.net/msf.483-485.953 ◽

2005 ◽

Vol 483-485 ◽

pp. 953-956 ◽

Cited By ~ 12

Author(s):

Tetsuya Hayashi ◽

Hideaki Tanaka ◽

Yoshio Shimoida ◽

Satoshi Tanimoto ◽

Masakatsu Hoshi

Keyword(s):

Leakage Current ◽

High Voltage ◽

Drift Region ◽

Heterojunction Diode ◽

Inductive Load ◽

Low Leakage ◽

Low Leakage Current ◽

Blocking Voltage ◽

Switching Characteristics ◽

P Type

We demonstrate a new high-voltage p+ Si/n- 4H-SiC heterojunction diode (HJD) by numerical simulation and experimental results. This HJD is expected to display good reverse recovery because of unipolar action similar to that of a SiC Schottky barrier diode (SBD) when forward biased. The blocking voltage of the HJD is almost equal to the ideal level in the drift region of n- 4H-SiC. In addition, the HJD has the potential for a lower reverse leakage current compared with the SBD. A HJD was fabricated with p+-type polycrystalline silicon on an n--type epitaxial layer of 4H-SiC. Measured reverse blocking voltage was 1600 V with low leakage current. Switching characteristics of the fabricated HJD showed nearly zero reverse recovery with an inductive load circuit.

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Analysis of Leakage Currents through PLD Grown Ultrathin a-LaGdO3 Based High-k Metal Gate Devices

MRS Proceedings ◽

10.1557/opl.2013.836 ◽

2013 ◽

Vol 1561 ◽

Author(s):

Shojan P. Pavunny ◽

Pankaj Misra ◽

Reji Thomas ◽

Ashok Kumar ◽

James F. Scott ◽

...

Keyword(s):

Leakage Current ◽

Forward Bias ◽

Bias Current ◽

Schottky Emission ◽

Silicon Substrates ◽

Low Leakage ◽

Low Leakage Current ◽

Trap Assisted Tunneling ◽

Assisted Tunneling ◽

P Type

ABSTRACTA detailed analysis of leakage current density-gate voltage measurements of gate stacks composed of PLD grown ultra thin films of LaGdO3 (LGO) on p-type silicon substrates with 8.4 Å EOT is presented. Temperature dependent leakage measurements revealed that forward bias current was dominated by Schottky emission over trap assisted tunneling below 1.2 MV/cm and quantum mechanical tunneling above this field. The physical origin of the reverse bias current was found to be a combination of Schottky emission and trap assisted tunneling. Low leakage current densities in the range from 2.3×10-3 to 29×10-3 A/cm2 were recorded for films with EOT from 1.8 to 0.8 nm, that are at least four or more orders below the ITRS specifications and its SiO2 competitors.

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ZnO-Pr6O11-Co3O4-TiO2-Based Ceramic Varistor Materials

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.434-435.389 ◽

2010 ◽

Vol 434-435 ◽

pp. 389-392

Author(s):

Hai Feng ◽

Zhi Jian Peng ◽

Cheng Biao Wang ◽

Zhi Qiang Fu ◽

He Zhuo Miao

Keyword(s):

Grain Growth ◽

Leakage Current ◽

Nonlinear Property ◽

Leakage Currents ◽

Nonlinear Properties ◽

Low Leakage ◽

Low Leakage Current ◽

Ceramic Varistor

The preparation and characterization of ZnO-Pr6O11-Co3O4-TiO2 (ZPCT) based varistor materials with different doping levels of TiO2 and Pr6O11 were investigated. The results reveal that: (1) TiO2 is an important additive, acting as an inhibitor of ZnO grain growth. The doping of appropriate amount of TiO2 can significantly improve the nonlinear properties and decreases the leakage current of the varistors, achieving a relatively high nonlinear exponent and low leakage current with 1.0 mol% TiO2 doped. (2) The oxide of Pr6O11 microstructurally plays the role of inhibition in grain growth. The doping of appropriate amount of Pr6O11 can improve the nonlinear property, and decrease the leakage currents of the varistors, acquiring the optimum results with 1.5 mol% Pr6O11 doped.

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Defect Elimination by MeV Ion Implantation

MRS Proceedings ◽

10.1557/proc-279-225 ◽

1992 ◽

Vol 279 ◽

Author(s):

S. Saito ◽

M. Kumagai ◽

T. Kondolt

Keyword(s):

Ion Implantation ◽

Leakage Current ◽

Defect Formation ◽

Boron Diffusion ◽

Current Increase ◽

Shallow Junction ◽

Low Leakage ◽

Low Leakage Current ◽

Junction Formation ◽

P Type

ABSTRACTIn the p-type shallow junction formation using B+ implantation, preamorphaization is an essential technique to suppress B+ channeling. The crucial problem in this process is defect formation at an amorphous-crystal(a-c) interface. We have demonstrated that MeV ion implantation is effective to reduce defects for shallow junction formation. F+ preimplantation at 40 KeV with 1×l015 cm−2 was effective to form p-type shallow junctions by B+ implantation at 10 KeV with 5×1015cm−2. However, defect formation induced boron diffusion and also leakage current increase. These problems were overcome by MeV ion implantation at 1 MeV F+ or Si+ with 5x×1015 cm−2, followed by rapid thermal annealing at 1000–1100°C for 10 seconds. In the P preimplanted samples, followed by MeV ion implantation, defects at the a-c interface can be reduced and an about 50 % shallower junction depth was obtained, compared with just B+ implanted samples. The results indicate that MeV ion implantation is effective to form a shallow junction with a low leakage current.

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High nonlinearity and low leakage current SnO2 varistor ceramics by co-doping with yttrium and tantalum

Materials Letters ◽

10.1016/j.matlet.2020.129120 ◽

2021 ◽

Vol 285 ◽

pp. 129120

Author(s):

Wenxin Liang ◽

Hongfeng Zhao ◽

Xiaoji Meng ◽

Shaohua Fan ◽

Qingyun Xie

Keyword(s):

Leakage Current ◽

Co Doping ◽

High Nonlinearity ◽

Low Leakage ◽

Low Leakage Current

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Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

MRS Proceedings ◽

10.1557/opl.2013.585 ◽

2013 ◽

Vol 1538 ◽

pp. 291-302

Author(s):

Edward Yi Chang ◽

Hai-Dang Trinh ◽

Yueh-Chin Lin ◽

Hiroshi Iwai ◽

Yen-Ku Lin

Keyword(s):

Low Power ◽

Leakage Current ◽

High Speed ◽

High Performance ◽

Gate Oxide ◽

Chemical Cleaning ◽

Low Leakage ◽

Low Leakage Current ◽

High K ◽

Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

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