Analysis of Leakage Currents through PLD Grown Ultrathin a-LaGdO3 Based High-k Metal Gate Devices

ABSTRACTA detailed analysis of leakage current density-gate voltage measurements of gate stacks composed of PLD grown ultra thin films of LaGdO3 (LGO) on p-type silicon substrates with 8.4 Å EOT is presented. Temperature dependent leakage measurements revealed that forward bias current was dominated by Schottky emission over trap assisted tunneling below 1.2 MV/cm and quantum mechanical tunneling above this field. The physical origin of the reverse bias current was found to be a combination of Schottky emission and trap assisted tunneling. Low leakage current densities in the range from 2.3×10-3 to 29×10-3 A/cm2 were recorded for films with EOT from 1.8 to 0.8 nm, that are at least four or more orders below the ITRS specifications and its SiO2 competitors.

Download Full-text

Temperature and Doping Dependency of Piezoresistivity in p-type Silicon

MRS Proceedings ◽

10.1557/proc-657-ee5.13 ◽

2000 ◽

Vol 657 ◽

Cited By ~ 1

Author(s):

Eivind Lund ◽

Terje G. Finstad

Keyword(s):

Leakage Current ◽

Negative Temperature ◽

Leakage Currents ◽

Micro Electro Mechanical Systems ◽

Type Silicon ◽

Low Leakage ◽

Low Leakage Current ◽

Wafer Thickness ◽

P Type ◽

Doping Profiles

ABSTRACTWe have performed new measurements of the temperature and doping dependency of the piezoresistive effect in p-type silicon. Piezoresistivity is one of the most common sensing principles of micro-electro-mechanical-systems (MEMS). Our measurements are performed in a specially designed setup based on the well-known 4 point bending technique. The samples are beams of full wafer thickness. To minimize leakage currents and to obtain uniform doping profiles, we have used SIMOX (Separation by IMplantation of OXygen) substrates with resistors defined in an epitaxial layer. Spreading resistance measurements show that the doping profiles are uniform with depth, while measurements of leakage current versus temperature indicate low leakage current. In this paper we present results for the doping concentration range from 1×1017 – 1×1020 cm−3 and the temperature range from –30 to 150 degrees Celsius. The results show a doping dependency of piezoresistivity well described by the current models. The measurements of the temperature dependency of the coefficients of piezoresistivity are compared to a linear model with a negative temperature coefficient whose absolute value decreases with increasing doping.

Download Full-text

Low-Leakage-Current Enhancement-Mode AlGaN/GaN Heterostructure Field-Effect Transistor Using p-Type Gate Contact

Japanese Journal of Applied Physics ◽

10.1143/jjap.45.l319 ◽

2006 ◽

Vol 45 (No. 11) ◽

pp. L319-L321 ◽

Cited By ~ 26

Author(s):

Norio Tsuyukuchi ◽

Kentaro Nagamatsu ◽

Yoshikazu Hirose ◽

Motoaki Iwaya ◽

Satoshi Kamiyama ◽

...

Keyword(s):

Leakage Current ◽

Field Effect ◽

Field Effect Transistor ◽

Enhancement Mode ◽

Low Leakage ◽

Low Leakage Current ◽

Effect Transistor ◽

Gan Heterostructure ◽

P Type

Download Full-text

Compact Spice Modeling and Design Optimization of Low Leakage a-Si:H TFTs for Large-Area Imaging Systems

MRS Proceedings ◽

10.1557/proc-507-415 ◽

1998 ◽

Vol 507 ◽

Cited By ~ 9

Author(s):

R.V.R. Murthy ◽

D. Pereira ◽

B. Park ◽

A. Nathan ◽

S.G. Chamberlain

Keyword(s):

Leakage Current ◽

Reverse Current ◽

Contact Layer ◽

Large Area ◽

Thermal Generation ◽

Low Leakage ◽

Low Leakage Current ◽

Trap Assisted Tunneling ◽

Current Characteristics ◽

Gap States

ABSTRACTWe present a SPICE model that takes into account the different mechanisms contributing to leakage current in hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs). The main sources of leakage current in these devices have been identified to be the parasitic reverse-biased p-i-n diode at the vicinity of the drain as well as diffusion of phosphorous atoms from micro-crystalline (n+ μc-Si:H) contact layer into the intrinsic a-Si:H region. The latter gives rise to ohmic conduction which dominates at very low drain voltages (< I V) and very low gate voltages (< 5 V). At higher gate voltages (5V ≤ VG ≤ 20 V), the reverse current of the parasitic p-i-n diode can be attributed to thermal generation of electrons from the valence to conduction bands through the mid-gap states in the a-Si:H. At even higher gate voltages (> 20 V), the reverse current is due to trap-assisted tunneling, whereby the electrons tunnel to the conduction band via the mid-gap states. A systematic characterization of TFTs with different a-Si:H layer thicknesses shows that the optimal thickness for low leakage current is around 50 nm. The bias dependent leakage current behavior has been modeled and implemented in SPICE using simple circuit elements based on voltage controlled current sources (VCCS). Simulated and measured reverse leakage current characteristics are in reasonable agreement.

Download Full-text

New High-Voltage Unipolar Mode p+ Si/n– 4H-SiC Heterojunction Diode

Materials Science Forum ◽

10.4028/www.scientific.net/msf.483-485.953 ◽

2005 ◽

Vol 483-485 ◽

pp. 953-956 ◽

Cited By ~ 12

Author(s):

Tetsuya Hayashi ◽

Hideaki Tanaka ◽

Yoshio Shimoida ◽

Satoshi Tanimoto ◽

Masakatsu Hoshi

Keyword(s):

Leakage Current ◽

High Voltage ◽

Drift Region ◽

Heterojunction Diode ◽

Inductive Load ◽

Low Leakage ◽

Low Leakage Current ◽

Blocking Voltage ◽

Switching Characteristics ◽

P Type

We demonstrate a new high-voltage p+ Si/n- 4H-SiC heterojunction diode (HJD) by numerical simulation and experimental results. This HJD is expected to display good reverse recovery because of unipolar action similar to that of a SiC Schottky barrier diode (SBD) when forward biased. The blocking voltage of the HJD is almost equal to the ideal level in the drift region of n- 4H-SiC. In addition, the HJD has the potential for a lower reverse leakage current compared with the SBD. A HJD was fabricated with p+-type polycrystalline silicon on an n--type epitaxial layer of 4H-SiC. Measured reverse blocking voltage was 1600 V with low leakage current. Switching characteristics of the fabricated HJD showed nearly zero reverse recovery with an inductive load circuit.

Download Full-text

Defect Elimination by MeV Ion Implantation

MRS Proceedings ◽

10.1557/proc-279-225 ◽

1992 ◽

Vol 279 ◽

Author(s):

S. Saito ◽

M. Kumagai ◽

T. Kondolt

Keyword(s):

Ion Implantation ◽

Leakage Current ◽

Defect Formation ◽

Boron Diffusion ◽

Current Increase ◽

Shallow Junction ◽

Low Leakage ◽

Low Leakage Current ◽

Junction Formation ◽

P Type

ABSTRACTIn the p-type shallow junction formation using B+ implantation, preamorphaization is an essential technique to suppress B+ channeling. The crucial problem in this process is defect formation at an amorphous-crystal(a-c) interface. We have demonstrated that MeV ion implantation is effective to reduce defects for shallow junction formation. F+ preimplantation at 40 KeV with 1×l015 cm−2 was effective to form p-type shallow junctions by B+ implantation at 10 KeV with 5×1015cm−2. However, defect formation induced boron diffusion and also leakage current increase. These problems were overcome by MeV ion implantation at 1 MeV F+ or Si+ with 5x×1015 cm−2, followed by rapid thermal annealing at 1000–1100°C for 10 seconds. In the P preimplanted samples, followed by MeV ion implantation, defects at the a-c interface can be reduced and an about 50 % shallower junction depth was obtained, compared with just B+ implanted samples. The results indicate that MeV ion implantation is effective to form a shallow junction with a low leakage current.

Download Full-text

High nonlinearity and low leakage current SnO2 varistor ceramics by co-doping with yttrium and tantalum

Materials Letters ◽

10.1016/j.matlet.2020.129120 ◽

2021 ◽

Vol 285 ◽

pp. 129120

Author(s):

Wenxin Liang ◽

Hongfeng Zhao ◽

Xiaoji Meng ◽

Shaohua Fan ◽

Qingyun Xie

Keyword(s):

Leakage Current ◽

Co Doping ◽

High Nonlinearity ◽

Low Leakage ◽

Low Leakage Current

Download Full-text

APPLICATION OF EPITAXIAL UNIPOLAR BARRIERS TO REDUCE NOISE CURRENTS IN PHOTODETECTORS

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156411006854 ◽

2011 ◽

Vol 20 (03) ◽

pp. 557-564

Author(s):

G. R. SAVICH ◽

J. R. PEDRAZZANI ◽

S. MAIMON ◽

G. W. WICKS

Keyword(s):

Leakage Current ◽

Surface Passivation ◽

Leakage Currents ◽

Type Region ◽

Surface Leakage Current ◽

Unipolar Barrier ◽

Trap Assisted Tunneling ◽

Assisted Tunneling ◽

Tunneling Currents ◽

Surface Leakage

Tunneling currents and surface leakage currents are both contributors to the overall dark current which limits many semiconductor devices. Surface leakage current is generally controlled by applying a post-epitaxial passivation layer; however, surface passivation is often expensive and ineffective. Band-to-band and trap assisted tunneling currents cannot be controlled through surface passivants, thus an alternative means of control is necessary. Unipolar barriers, when appropriately applied to standard electronic device structures, can reduce the effects of both surface leakage and tunneling currents more easily and cost effectively than other methods, including surface passivation. Unipolar barriers are applied to the p -type region of a conventional, MBE grown, InAs based pn junction structures resulting in a reduction of surface leakage current. Placing the unipolar barrier in the n -type region of the device, has the added benefit of reducing trap assisted tunneling current as well as surface leakage currents. Conventional, InAs pn junctions are shown to exhibit surface leakage current while unipolar barrier photodiodes show no detectable surface currents.

Download Full-text

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

MRS Proceedings ◽

10.1557/opl.2013.585 ◽

2013 ◽

Vol 1538 ◽

pp. 291-302

Author(s):

Edward Yi Chang ◽

Hai-Dang Trinh ◽

Yueh-Chin Lin ◽

Hiroshi Iwai ◽

Yen-Ku Lin

Keyword(s):

Low Power ◽

Leakage Current ◽

High Speed ◽

High Performance ◽

Gate Oxide ◽

Chemical Cleaning ◽

Low Leakage ◽

Low Leakage Current ◽

High K ◽

Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

Download Full-text