Shallow Silicided Junctions for VLSI Cmos Transistors by Furnace and Rapid Thermal Processing

As a result of device scaling very shallow low resistance diffusions are required for VLSI CMOS fabrication. This paper describes a technique for their formation using silicon implantation for preamorphisation, counterdoping arsenic implantation and overall boron fluoride implantation for the sources and drains of the n- and p-channel transistors. Platinum silicidation has been used to reduce diffusion and polysilicon sheet resistances to 8Q/square. Activation of the shallow diffusions has been achieved either by furnace annealing (FA) or rapid thermal annealing (RTA) in the range 900°C to 1100 °C. Materials results are discussed including TTEM, SIMS and SR profiling. The suitability of the technique for VLSI CMOS applications is demonstrated by the fabrication of sub-micron transistors. With larger wafer diameters (>5') the FA conditions considered are not practicable owing to ramped diffusion effects which lead to deeper junctions. Hence RTA is necessary: optimum conditions found were 1100 °C for 10 seconds when device performance equivalent to or better than FA can be achieved.