Effect of Microstructure and Dielectric Materials on Stress-Induced Damages in Damascene Cu/Low-k Interconnects

2005 ◽  
Vol 863 ◽  
Author(s):  
Young-Chang Joo ◽  
Jong-Min Paik ◽  
Jung-Kyu Jung

AbstractThe line width dependence of stress in damascene Cu was examined experimentally as well as with a numerical simulation. The measured hydrostatic stress was found to increase with increasing line width. The larger stress in an interconnect with large dimension is attributed to the larger grain size, which induce higher growth stress in addition to thermomechanical stress. A stress model based on microstructure was constructed and the contribution of the growth and thermal stress of the damascene lines were quantified using finite element analysis. It was found that the stress of the via is lower than that of wide lines when both the growth stress and thermal stress were considered. This stress gradient between via and line, which is the driving force of vacancy diffusion, is larger when the low-k with lower stiffness and higher thermal expansion is used for dielectric layer. For this reason, the Cu/low-k can be more vulnerable to stress-induced voiding.

2003 ◽  
Vol 795 ◽  
Author(s):  
Jong-Min Paik ◽  
Hyun Park ◽  
Ki-Chul Park ◽  
Young-Chang Joo

ABSTRACTVarious low-k materials are being pursued as dielectric materials for future interconnects. However, poor thermo-mechanical properties of low-k materials cause tremendous reliability concerns, thus the proper materials for integration with Cu are not suggested yet. In this study, the line width and spacing dependence of damascene Cu lines embedded by TEOS and low-k materials (CORAL) was analyzed using x-ray diffraction. Generally, the hydrostatic stress of Cu/TEOS was greater than that of Cu/CORAL, while the opposite for von-Mises stress. Using a three-dimensional finite analysis (FEA), the effect of low-k materials on the stress and its distribution in via-line structures of dual damascene Cu interconnects was studied. In the case of Cu/TEOS, the hydrostatic stress was concentrated at the via and on the top of the lines, where it was suspected that the void would nucleate. On the other hand, in the via-line structures integrated with organic low-k materials, large von-Mises stress was maintained in the via. Therefore, the deformation of via, rather than voiding, may be the main failure mode in the interconnects with low-k materials.


2006 ◽  
Vol 504 (1-2) ◽  
pp. 284-287 ◽  
Author(s):  
Jong-Min Paik ◽  
Il-Mok Park ◽  
Young-Chang Joo

2013 ◽  
Vol 562-565 ◽  
pp. 1471-1476 ◽  
Author(s):  
Ya Ting Huang ◽  
Chun Ling Meng ◽  
Nian Peng Wu ◽  
Xiu Ping Dong ◽  
Xin Chun Lu

Megasonic cleaning has been one of the most successful techniques for Cu/low-k interconnects post-CMP cleaning. The structural deformation and stress of Cu and low-k materials in megasonic cleaning are examined with finite element method (FEM). The maximum stress is concentrated in the binding area between Cu and low-k. With decrease of Cu line width, the maximum stress increases and the max value exceeds the yield strength of Cu which results in the plastic deformation. The increasing frequency will change the bubble collision times. Therefore the fatigue is potential. The maximum displacement moves from center to the sides of top surface with increase of line width. When the line width is 25nm, the deformation is the largest.


2006 ◽  
Vol 914 ◽  
Author(s):  
Seung-Hyun Rhee ◽  
Conal E. Murray ◽  
Paul R. Besser

AbstractThe measurement and control of the stress state in BEOL interconnects are important to ensure structural integrity and long term reliability of integrated circuits. Thermal stress in interconnects is determined by the thermal-mechanical properties of Cu lines, substrate, and dielectric materials. The effect of BEOL stacks on thermal stress characteristics of Cu lines were investigated using X-ray diffraction stress measurements. The stress characteristics of M1 and M4 level interconnects in full low-k and low-k/oxide hybrid dielectric stacks were evaluated, and the results indicated reduced substrate confinement and an increased impact of the dielectric material on in-plane stresses in higher level interconnects. The effects of dielectric stack and material properties were examined and the implication in the stresses of multilevel interconnects are discussed.


2019 ◽  
Vol 141 (1) ◽  
Author(s):  
Lei Wang ◽  
Jun Wang ◽  
Fei Xiao

A chip with 40 nm technology node and beyond generally incorporates low-k/ultra-low-k (LK/ULK) dielectric materials and copper traces in the back end of line (BEOL) to improve its electrical performance. Owing to the fragile low-k/ultra-low-k materials, the BEOL becomes vulnerable to external loads. When a copper pillar bump (CPB) above the BEOL sustains a shear force due to thermal mismatch between the components, failures occur in the microstructures of BEOL, especially in low-k materials. We fabricated CPBs on the chips and investigated fractures in the BEOL by a shear test approach. The shear speed and shear height are varied to examine their effects. The tested samples were analyzed via focused ion beam (FIB) and scanning electron microscope (SEM) to reveal the microstructures degradation or breaks in the BEOL, and they are classified into three kinds of failure modes. Assisted by a finite element analysis (FEA), the failure mechanism was explained and associated with the failure modes. The studies showed that the shear speed has a little influence on the maximum shear stress, but the increase of shear height leads to more fractures in the low-k materials. It indicated that decreasing the height of CPBs is helpful for reducing destruction risk of the BEOL under the thermomechanical loads. Based on a parametric study for shearing test simulation of a single CPB, the modulus and thickness of polyimide (PI) were found a larger impact on the stresses in the low-k material layer, but the modulus of low-k materials has a smaller effect on the stress. Generally, the shear test of a CPB can help to evaluate the integrity of BEOL in a chip.


2020 ◽  
Vol 64 (1-4) ◽  
pp. 1337-1345
Author(s):  
Chuan Zhao ◽  
Feng Sun ◽  
Junjie Jin ◽  
Mingwei Bo ◽  
Fangchao Xu ◽  
...  

This paper proposes a computation method using the equivalent magnetic circuit to analyze the driving force for the non-contact permanent magnet linear drive system. In this device, the magnetic driving force is related to the rotation angle of driving wheels. The relationship is verified by finite element analysis and measuring experiments. The result of finite element simulation is in good agreement with the model established by the equivalent magnetic circuit. Then experiments of displacement control are carried out to test the dynamic characteristic of this system. The controller of the system adopts the combination control of displacement and angle. The results indicate that the system has good performance in steady-state error and response speed, while the maximum overshoot needs to be reduced.


Author(s):  
Xiandong Zhou ◽  
Christoph Reimuth ◽  
Peter Stein ◽  
Bai-Xiang Xu

AbstractThis work presents a regularized eigenstrain formulation around the slip plane of dislocations and the resultant non-singular solutions for various dislocation configurations. Moreover, we derive the generalized Eshelby stress tensor of the configurational force theory in the context of the proposed dislocation model. Based on the non-singular finite element solutions and the generalized configurational force formulation, we calculate the driving force on dislocations of various configurations, including single edge/screw dislocation, dislocation loop, interaction between a vacancy dislocation loop and an edge dislocation, as well as a dislocation cluster. The non-singular solutions and the driving force results are well benchmarked for different cases. The proposed formulation and the numerical scheme can be applied to any general dislocation configuration with complex geometry and loading conditions.


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