Study on BEOL Failures in a Chip by Shear Tests of Copper Pillar Bumps

2019 ◽  
Vol 141 (1) ◽  
Author(s):  
Lei Wang ◽  
Jun Wang ◽  
Fei Xiao

A chip with 40 nm technology node and beyond generally incorporates low-k/ultra-low-k (LK/ULK) dielectric materials and copper traces in the back end of line (BEOL) to improve its electrical performance. Owing to the fragile low-k/ultra-low-k materials, the BEOL becomes vulnerable to external loads. When a copper pillar bump (CPB) above the BEOL sustains a shear force due to thermal mismatch between the components, failures occur in the microstructures of BEOL, especially in low-k materials. We fabricated CPBs on the chips and investigated fractures in the BEOL by a shear test approach. The shear speed and shear height are varied to examine their effects. The tested samples were analyzed via focused ion beam (FIB) and scanning electron microscope (SEM) to reveal the microstructures degradation or breaks in the BEOL, and they are classified into three kinds of failure modes. Assisted by a finite element analysis (FEA), the failure mechanism was explained and associated with the failure modes. The studies showed that the shear speed has a little influence on the maximum shear stress, but the increase of shear height leads to more fractures in the low-k materials. It indicated that decreasing the height of CPBs is helpful for reducing destruction risk of the BEOL under the thermomechanical loads. Based on a parametric study for shearing test simulation of a single CPB, the modulus and thickness of polyimide (PI) were found a larger impact on the stresses in the low-k material layer, but the modulus of low-k materials has a smaller effect on the stress. Generally, the shear test of a CPB can help to evaluate the integrity of BEOL in a chip.

Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.


Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.


Author(s):  
H. J. Bender ◽  
R. A. Donaton

Abstract The characteristics of an organic low-k dielectric during investigation by focused ion beam (FIB) are discussed for the different FIB application modes: cross-section imaging, specimen preparation for transmission electron microscopy, and via milling for device modification. It is shown that the material is more stable under the ion beam than under the electron beam in the scanning electron microscope (SEM) or in the transmission electron microscope (TEM). The milling of the material by H2O vapor assistance is strongly enhanced. Also by applying XeF2 etching an enhanced milling rate can be obtained so that both the polymer layer and the intermediate oxides can be etched in a single step.


Author(s):  
Frank Altmann ◽  
Christian Grosse ◽  
Falk Naumann ◽  
Jens Beyersdorfer ◽  
Tony Veches

Abstract In this paper we will demonstrate new approaches for failure analysis of memory devices with multiple stacked dies and TSV interconnects. Therefore, TSV specific failure modes are studied on daisy chain test samples. Two analysis flows for defect localization implementing Electron Beam Induced Current (EBAC) imaging and Lock-in-Thermography (LIT) as well as adapted Focused Ion Beam (FIB) preparation and defect characterization by electron microscopy will be discussed. The most challenging failure mode is an electrical short at the TSV sidewall isolation with sub-micrometer dimensions. It is shown that the leakage path to a certain TSV within the stack can firstly be located by applying LIT to a metallographic cross section and secondly pinpointing by FIB/SEM cross-sectioning. In order to evaluate the potential of non-destructive determination of the lateral defect position, as well as the defect depth from only one LIT measurement, 2D thermal simulations of TSV stacks with artificial leakages are performed calculating the phase shift values per die level.


2010 ◽  
Vol 1249 ◽  
Author(s):  
George Andrew Antonelli ◽  
Gengwei Jiang ◽  
Mandyam Sriram ◽  
Kaushik Chattopadhyay ◽  
Wei Guo ◽  
...  

AbstractOrganosilicate materials with dielectric constants (k) ranging from 3.0 to 2.2 are in production or under development for use as interlayer dielectric materials in advanced interconnect logic technology. The dielectric constant of these materials is lowered through the addition of porosity which lowers the film density, making the patterning of these materials difficult. The etching kinetics and surface roughening of a series of low-k dielectric materials with varying porosity and composition were investigated as a function of ion beam angle in a 7% C4F8/Ar chemistry in an inductively-coupled plasma reactor. A similar set of low-k samples were patterned in a single damascene scheme. With a basic understanding of the etching process, we will show that it is possible to proactively design a low-k material that is optimized for a given patterning. A case study will be used to illustrate this point.


Author(s):  
Alan Turnbull

In many applications, corrosion pits act as precursors to cracking, but qualitative and quantitative prediction of damage evolution has been hampered by lack of insights into the process by which a crack develops from a pit. An overview is given of recent breakthroughs in characterization and understanding of the pit-to-crack transition using advanced three-dimensional imaging techniques such as X-ray computed tomography and focused ion beam machining with scanning electron microscopy. These techniques provided novel insights with respect to the location of crack development from a pit, supported by finite-element analysis. This inspired a new concept for the role of pitting in stress corrosion cracking based on the growing pit inducing local dynamic plastic strain, a critical factor in the development of stress corrosion cracks. Challenges in quantifying the subsequent growth rate of the emerging small cracks are then outlined with the potential drop technique being the most viable. A comparison is made with the growth rate for short cracks (through-thickness crack in fracture mechanics specimen) and long cracks and an electrochemical crack size effect invoked to rationalize the data.


Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.


2012 ◽  
Vol 1433 ◽  
Author(s):  
Andrew A. Woodworth ◽  
Ali Sayir ◽  
Philip G. Neudeck ◽  
Balaji Raghothamachar ◽  
Michael Dudley

ABSTRACTCommercially available bulk silicon carbide (SiC) has a high number (>2000/cm2) of screw dislocations (SD) that have been linked to degradation of high-field power device electrical performance properties. Researchers at the NASA Glenn Research Center have proposed a method to mass-produce significantly higher quality bulk SiC. In order for this bulk growth method to become reality, growth of long single crystal SiC fibers must first be achieved. Therefore, a new growth method, Solvent-Laser Heated Floating Zone (Solvent-LHFZ), has been implemented. While some of the initial Solvent-LHFZ results have recently been reported, this paper focuses on further characterization of grown crystals and their growth fronts. To this end, secondary ion mass spectroscopy (SIMS) depth profiles, cross section analysis by focused ion beam (FIB) milling and mechanical polishing, and orientation and structural characterization by X-ray transmission Laue diffraction patterns and X-ray topography were used. Results paint a picture of a chaotic growth front, with Fe incorporation dependant on C concentration.


Polymers ◽  
2021 ◽  
Vol 13 (16) ◽  
pp. 2640
Author(s):  
Raz Samira ◽  
Atzmon Vakahi ◽  
Rami Eliasy ◽  
Dov Sherman ◽  
Noa Lachman

Focused Ion Beam (FIB) is one of the most common methods for nanodevice fabrication. However, its implications on mechanical properties of polymers have only been speculated. In the current study, we demonstrated flexural bending of FIB-milled epoxy nanobeam, examined in situ under a transmission electron microscope (TEM). Controllable displacement was applied, while real-time TEM videos were gathered to produce morphological data. EDS and EELS were used to characterize the compositions of the resultant structure, and a computational model was used, together with the quantitative results of the in situ bending, to mechanically characterize the effect of Ga+ ions irradiation. The damaged layer was measured at 30 nm, with high content of gallium (40%). Examination of the fracture revealed crack propagation within the elastic region and rapid crack growth up to fracture, attesting to enhanced brittleness. Importantly, the nanoscale epoxy exhibited a robust increase in flexural strength, associated with chemical tempering and ion-induced peening effects, stiffening the outer surface. Young’s modulus of the stiffened layer was calculated via the finite element analysis (FEA) simulation, according to the measurement of 30 nm thickness in the STEM and resulted in a modulus range of 30–100 GPa. The current findings, now established in direct measurements, pave the way to improved applications of polymers in nanoscale devices to include soft materials, such as polymer-based composites and biological samples.


Author(s):  
Prabjit Singh ◽  
Larry Palmer ◽  
James Demarest ◽  
Larry Fischer ◽  
George Hutt ◽  
...  

Abstract Contrary to known art, we have discovered that lubricated tin-silver connectors have better electrical performance and are more reliable than lubricated silver-silver connectors under high-current and high-vibration conditions. The antifretting lubricant, that enhances the performance and reliability of the tin-silver connectors, is a grease consisting of a hydrocarbon oil in a nano-sized silica-particle base. Focused ion beam and scanning electron microscopy were used to understand the contact degradation mechanism. The superior electrical performance and reliability of the lubricated tin-silver connectors is due to a mechanism that replaces the tin plating from the contact surface with a coating of silver. The removal of the tin plating may be due to wear and the replacement by the silver coating may be due to an electrochemical displacement reaction.


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