Effects of BEOL Stack on Thermal Mechanical Stress of Cu Lines

2006 ◽  
Vol 914 ◽  
Author(s):  
Seung-Hyun Rhee ◽  
Conal E. Murray ◽  
Paul R. Besser
Keyword(s):  
Thermal Stress ◽  
Integrated Circuits ◽  
Structural Integrity ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
X Ray Diffraction ◽  
And Control ◽  
Measurement And Control ◽  
Low K

AbstractThe measurement and control of the stress state in BEOL interconnects are important to ensure structural integrity and long term reliability of integrated circuits. Thermal stress in interconnects is determined by the thermal-mechanical properties of Cu lines, substrate, and dielectric materials. The effect of BEOL stacks on thermal stress characteristics of Cu lines were investigated using X-ray diffraction stress measurements. The stress characteristics of M1 and M4 level interconnects in full low-k and low-k/oxide hybrid dielectric stacks were evaluated, and the results indicated reduced substrate confinement and an increased impact of the dielectric material on in-plane stresses in higher level interconnects. The effects of dielectric stack and material properties were examined and the implication in the stresses of multilevel interconnects are discussed.

Study of Porous Silica Based Films as Low-k Dielectric Material and their Interface with Copper Metallization

2002 ◽  
Vol 716 ◽  
Author(s):  
Ilanit Fisher ◽  
Wayne D. Kaplan ◽  
Moshe Eizenberg ◽  
Michael Nault ◽  
Timothy Weidman
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Hydrogen Plasma ◽  
Porous Silica ◽  
Film Deposition ◽  
Copper Metallization ◽  
High Porosity ◽  
Tem Analysis ◽  
Chip Technology ◽  
Low K

AbstractThe success of future gigascale integrated circuits (IC) chip technology depends critically upon the reduction of the interconnects RC delay time. This calls for the development of new low dielectric constant (low-k) insulators, and for work on their integration with lower resistivity copper metallization.A porous silica based film prepared by surfactant templated self-assembly spin-on deposition (SOD) is an attractive candidate as a low-k material. In this research we have studied the structure, chemical composition and bonding of the film and its interface with copper metallization. The decomposition and vaporization of the surfactant in the last step of film deposition resulted in a film with an amorphous structure, as determined by XRD and TEM analysis. Its high porosity (35-58%) was confirmed by XRR and RBS measurements. XPS analysis of the Si2p transition indicated three types of bonding: Si-O, O-Si-C and Si-C. The bonding characteristics were also investigated by FTIR analysis. The effect of a hydrogen plasma post-treatment process on the film topography and bonding was determined by AFM and XPS, respectively. It was found that direct H2 plasma exposure significantly affected the surface roughness of the film and type of chemical bonding. The structure and properties of various PECVD deposited capping layers were also studied, as was the interface between the porous dielectric and Ta, TaxN and Cu (PVD deposited films) after annealing at 200-700°C in vacuum environment for 30 min. At temperatures up to 500°C, no significant diffusion of Cu or Ta into the porous film was detected, as determined by RBS. No copper penetration was detected up to 700°C, according to AES and SIMS analysis. However, at 700°C copper dewetting occurred when it was deposited directly on the porous silica based film.

scholarly journals Incomplete Assessment of Experimental Cytoprotectants in Rodent Ischemia Studies

2003 ◽  
Vol 30 (4) ◽  
pp. 368-374 ◽  
Author(s):  
Suzanne B. DeBow ◽  
Darren L. Clark ◽  
Crystal L. MacLellan ◽  
Frederick Colbourne
Keyword(s):  
Focal Ischemia ◽  
Measured Temperature ◽  
Survival Times ◽  
Experimental Neurology ◽  
Clinical Conditions ◽  
And Control ◽  
Measurement And Control ◽  
Age And Sex ◽  
Leading Journals

Background:Inadequate preclinical testing (e.g., rodent studies) has been partly blamed for the failure of many cytoprotectants to effectively treat stroke in humans. For example, some drugs went to clinical trial without rigorous functional and histological assessment over long survival times. In this study, we characterized recent experimental practices in rodent cytoprotection experiments to determine whether the limitations of early studies have been rectified.Methods:We identified 138 rodent cytoprotection studies published in several leading journals (Journal of Neuroscience, Stroke, Journal of Cerebral Blood Flow and Metabolism and Experimental Neurology) for 2000 - 2002 and compared these to those published in 1990. From each study we determined the ischemia model, age and sex of the animal, the histological and functional endpoints used, and the methodology used to assess intra- and postischemic temperature.Results:Ninety-eight percent of recent studies used young adult rodents and most used males. Most studies (60%) did not assess functional outcome and survival times were often ≤ 48 hr (66%) for focal ischemia and ≤ 7 days (80%) for global ischemia. Over 60% of the experiments relied solely upon rectal temperature during ischemia and only 32.6% of ischemia studies measured temperature after surgery. The 1990 data were similar.Conclusion:Many investigators ignore the need to assess long-term functional and histological outcome and do not accurately represent clinical conditions of ischemia (e.g., use of aged animals). In addition, intra- and postischemic temperature measurement and control is frequently neglected or inadequately performed. Further clinical failures are likely.

Methods And Needs For Low K Material Research

1995 ◽  
Vol 381 ◽  
Author(s):  
Chiu H. Ting ◽  
Thomas E. Seidel
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Material Research ◽  
Material Development ◽  
Device Reliability ◽  
New Material ◽  
Speed Up ◽  
Low K

AbstractFor several years the industry has recognized the need of developing low k dielectric material and high conductivity metal for high performance interconnect. Low k dielectric will impact both power and delay favorably, while higher conductivity metal will reduce delay time. In order to be useful, new low k dielectric materials must be carefully characterized for their electrical, chemical, thermal and mechanical properties. In addition, their impact on process integration, fabrication cost and device reliability must also be considered. Since the gestation period for introducing a new material is very long, a set of standard testing methodologies are required to speed up the development process. This review will discuss various material options and the progress of material development and characterization methodologies. Example results will be provided for assessing these parameters.

Long term developments in switching

1978 ◽  
Vol 289 (1356) ◽  
pp. 65-77
Keyword(s):  
Integrated Circuits ◽  
Distributed Control ◽  
Optical Transmission ◽  
Digital Transmission ◽  
Control Techniques ◽  
Control Functions ◽  
Open Questions ◽  
The Common ◽  
And Control

Developments are considered under the headings (i) connection techniques, (ii) control techniques, (hi) interaction of switching and transmission techniques, (iv) facilities offered, and (v) connecting network topology. In each topic, there are open questions. The major forecasts are: (i) the extensive use of electronic digital multiplex connecting networks, compatible with digital transmission systems; (ii) the introduction of optical connecting techniques, which offer both compatibility with optical transmission and some interesting new possibilities for the size and configuration of switches; (iii) the extensive use of stored program control; (iv) the supplementation of central processors by distributed control techniques for the common operational procedures, probably using microprocessors; and (v) the widespread use of semiconductor integrated circuits both for connection and control functions.

Novel Materials as Interlayer Low-K Dielectrics for CMOS Interconnect Applications

2011 ◽  
Vol 110-116 ◽  
pp. 5380-5383
Author(s):  
Tejas R. Naik ◽  
Veena R. Naik ◽  
Nisha P. Sarwade
Keyword(s):  
Dielectric Constant ◽  
Integrated Circuits ◽  
Dielectric Materials ◽  
Low Dielectric Constant ◽  
Interlayer Dielectric ◽  
Novel Materials ◽  
Low Dielectric ◽  
Processing Properties ◽  
New Generation ◽  
Low K

Scaling down the integrated circuits has resulted in the arousal of number of problems like interaction between interconnect, crosstalk, time delay etc. These problems can be overcome by new designs and by use of corresponding novel materials, which may be a solution to these problems. In the present paper we try to put forward very recent development in the use of novel materials as interlayer dielectrics (ILDs) having low dielectric constant (k) for CMOS interconnects. The materials presented here are porous and hybrid organo-inorganic new generation interlayer dielectric materials possessing low dielectric constant and better processing properties.

Process Integration issues for Interlevel Dielectric Materials for Sub-quarter Micron Silicon Integrated Circuits

1998 ◽  
Vol 511 ◽  
Author(s):  
Vijay Parihar ◽  
R. Singh
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Process Integration ◽  
Dielectric Materials ◽  
New Approach ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Silicon Integrated Circuits ◽  
Processing Techniques ◽  
Low K

ABSTRACTThe continued miniaturization towards sub-quarter micron feature size mandates the search for low dielectric constant interlayer dielectric materials. A large number of materials and processing techniques has been suggested, but so far none of the proposed dielectric materials as well as processing techniques have been integrated into standard integrated circuit processing. In this paper, a new approach has been formulated for integration of low-k dielectric materials for future integrated circuits.

Effect of Microstructure and Dielectric Materials on Stress-Induced Damages in Damascene Cu/Low-k Interconnects

2005 ◽  
Vol 863 ◽  
Author(s):  
Young-Chang Joo ◽  
Jong-Min Paik ◽  
Jung-Kyu Jung
Keyword(s):  
Thermal Stress ◽  
Line Width ◽  
Driving Force ◽  
Hydrostatic Stress ◽  
Stress Gradient ◽  
Dielectric Materials ◽  
Growth Stress ◽  
Element Analysis ◽  
Thermomechanical Stress ◽  
Low K

AbstractThe line width dependence of stress in damascene Cu was examined experimentally as well as with a numerical simulation. The measured hydrostatic stress was found to increase with increasing line width. The larger stress in an interconnect with large dimension is attributed to the larger grain size, which induce higher growth stress in addition to thermomechanical stress. A stress model based on microstructure was constructed and the contribution of the growth and thermal stress of the damascene lines were quantified using finite element analysis. It was found that the stress of the via is lower than that of wide lines when both the growth stress and thermal stress were considered. This stress gradient between via and line, which is the driving force of vacancy diffusion, is larger when the low-k with lower stiffness and higher thermal expansion is used for dielectric layer. For this reason, the Cu/low-k can be more vulnerable to stress-induced voiding.

Surfactants in Controlling Removal Rates and Selectivity in Barrier Slurry for Cu CMP

2007 ◽  
Vol 991 ◽  
Author(s):  
Jinru Bian
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Removal Rate ◽  
Leading Edge ◽  
Dielectric Surface ◽  
Wafer Surface ◽  
Capping Layer ◽  
Charge Interaction ◽  
High Removal Rate ◽  
Low K

ABSTRACTLeading edge integrated circuits (ICs) are complicated structures designed to have up to 3 capping layers above a low k dielectric material. The upper capping layer may use TEOS and/or silicon nitride (SiN), while the lower one may use silicon carbon nitride (SiCN), silicon carbide (SiC), or carbon doped oxide (CDO) immediately above the low k dielectric. Therefore, a barrier slurry for copper CMP, in addition to exhibiting a high removal rate of the barrier, must be able to remove the upper capping layer and stop at the underlying dielectric surface.We have developed a slurry family that can effectively remove TaN, TEOS, SiN, CDO, and/or SiCN, or any combination of these films, or can stop at any one or two film surfaces of TEOS, SiN, CDO, SiCN, and SiC, depending on the specific slurry design. Removal rate control is achieved by one or two additives. One of the additives is an anionic surfactant. When selecting a surfactant, the surfactant hydrophobicity and charge interaction between the surfactant and the wafer surface are two important factors to be considered. This report discusses these two factors in selecting a proper surfactant for a specific slurry application.

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