scholarly journals Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

2017 ◽  
Author(s):  
Pooran Singh ◽  
Santosh Vishvakarma
Keyword(s):  
Internet Of Things ◽  
Power Consumption ◽  
Low Power ◽  
Leakage Power ◽  
Static Noise Margin ◽  
Ultra Low Power ◽  
Iot Applications ◽  
Noise Margin ◽  
Standby Mode ◽  
Static Noise

An ultra-low power (ULP), power gated static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates in sub-threshold voltage ranges from 300mV to 500mV. The proposed SRAM has tendency to operate in low supply voltages with high static and dynamic noise margins. The IoT application involves battery enabled low leakage memory architecture in subthreshold regime which has low power consumption. Therefore, to improve power consumption along with better cell stability, a power gated 10T SRAM is presented. The proposed cell uses a power gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the schmitt triggering and read decoupling of 10T SRAM the static and dynamic behavior in read, write and standby mode has shown enhanced tolerance at different process, voltage and temperature (PVT) conditions. The proposed SRAM shows better results in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write-ability or write trip point (WTP), read-write energy and dynamic read margin (DRM). Further, these parameters are observed at 8-Kilo bit (Kb) and compared with already existing SRAM architectures. It is observed that the leakage power is reduced by 1/81×, 1/75× of the conventional 6T (C6T) SRAM and read decoupled 8T (RD8T) SRAM, respectively at 300mV VDD. On the contrary, RSNM, WSNM, WTP and DRM values are improved by 3×, 2×, 11.11% and 31.8% as compared to C6T SRAM, respectively. Similarly, proposed 10T has 1.48×, 25% and 9.75% better RSNM, WSNM and WTP values as compared to RD8T SRAM, respectively at 300mV VDD.

Variability aware FinFET SRAM cell with improved stability and power for low power applications

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 196-207
Author(s):  
Shilpi Birla
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Leakage Power ◽  
Static Noise Margin ◽  
Content Type ◽  
Noise Margin ◽  
Sram Cell ◽  
Memory Circuits ◽  
The Stability ◽  
Static Noise

Purpose Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits. Design/methodology/approach In this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. Findings The cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384  mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed. Research limitations/implications The FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used. Practical implications SRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array. Social implications The cell can be used for SRAM memory for low power consumptions. Originality/value The work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

Energy-efficient data retention in D flip-flops using STT-MTJ

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 229-241 ◽  
Author(s):  
Kanika Monga ◽  
Nitin Chaturvedi ◽  
S. Gurunarayanan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Leakage Power ◽  
Total Power ◽  
System State ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Content Type ◽  
Total Power Consumption ◽  
Standby Mode

Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention. Design/methodology/approach The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state. Findings A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption. Originality/value Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

scholarly journals Restoration circuits for Low power Reduce Swing of 6T and 8T SRAM Cell With Improved Read and Write Margins

2021 ◽  
Vol 7 ◽  
pp. 22-34
Author(s):  
Vinod Kumar ◽  
Ram Murti Rawat
Keyword(s):  
Low Power ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Equivalent Time ◽  
Sram Cell ◽  
Section Viii ◽  
Static Noise

A paper that examines the factors thataffect the Static Noise Margin (SNM) of a StaticRandom Access memories. At an equivalent time,they specialise in optimizing Read and Writeoperation of 8T SRAM cell which is best than 6TSRAM cell Using Swing Restoration Dual NodeVoltage. The read and Write operation and improveStability analysis. This SRAM technique on thecircuit or architecture level is required to improveread and write operation. during this paperComparative Analysis of 6T and 8T SRAM Cellswith Improved Read and Write Margin is completedfor 180 nm Technology with Cadence Virtuososchematics Tool.This Paper is organized as follows: thecharacteristics of 6T SRAM cell are described arerepresented in section VIII. In section IX, proposed8T SRAM cell is described. In section X, Standard8T SRAM cell is described. Section XI includes thesimulation results which give comparison of variousparameters of 6T and 8T SRAM cells. In Section XIISimulation Results and DC analysis and sectionXIII conclusion the work.

scholarly journals Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

2020 ◽  
Vol 2020 ◽  
pp. 1-7
Author(s):  
Mathan Natarajamoorthy ◽  
Jayashri Subbiah ◽  
Nurul Ezaila Alias ◽  
Michael Loong Peng Tan
Keyword(s):  
Power Consumption ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Graphene Nanoribbon ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Average Power Consumption ◽  
Sram Design ◽  
Effect Transistor ◽  
Static Noise

The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.

A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability

2019 ◽  
Vol 29 (05) ◽  
pp. 2050067
Author(s):  
S. R. Mansore ◽  
R. S. Gamad ◽  
D. K. Mishra
Keyword(s):  
High Performance ◽  
Model Simulation ◽  
Random Access ◽  
Leakage Power ◽  
Access Memory ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Operation Characteristics ◽  
Static Noise

Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32[Formula: see text]nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5[Formula: see text] and 1.06[Formula: see text] higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4[Formula: see text]V. Write static noise margin (WSNM) of the proposed design is 1.65[Formula: see text], 1.71[Formula: see text] and 1.77[Formula: see text] larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108[Formula: see text] and 0.81[Formula: see text] as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40[Formula: see text] lesser read power as compared to PPN10T cell at 0.4[Formula: see text]V. Leakage power of the proposed cell is 0.35[Formula: see text] of C6T cell at 0.4[Formula: see text]V. Proposed 11T cell occupies 1.65[Formula: see text] larger area as compared to that of conventional 6T.

A compact and low-power SRAM with improved read static noise margin

2008 ◽  
Author(s):  
Cihun-Siyong Alex Gong ◽  
Ci-Tong Hong ◽  
Kai-Wen Yao ◽  
Muh-Tian Shiue ◽  
Kuo-Hsing Cheng
Keyword(s):  
Low Power ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Static Noise

scholarly journals Energy Efficient SRAM

2019 ◽  
Vol 8 (9) ◽  
pp. 1086-1091
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Static Noise Margin ◽  
Noise Margin ◽  
And Performance ◽  
The Stability ◽  
Static Noise

Memories are an essential unit of any digital circuit, thus their power consumption must be considered during the designing process of the cells. To improve performance, reduce delay and increase stability, it is advisable to decrease the power consumed by the memory. Due to high demand of speed, high performance, there’s a need to decrease the size of the device, thereby increasing the devices placed per chip. This high integration makes chips more complex but improves device performance. Design of SRAM cells with speed and low power is crucial so as to replace DRAMs. The layout of SRAM has advanced to meet the requirements of the present industry in accordance with parameters like delay, power consumption and stability etc. This paper presents the aim of analyzing different technologies used to make SRAM more efficient in terms of parameters such as static noise margin, latency and dissipation of power. The stability investigation of SRAM cells are usually derived from the Static Noise Margin (SNM) analysis. Here we observe a SRAM design which has used dynamic logic and pass transistor logic. We further study the effects made on this design by employing various technologies such as AVL-S, AVL-G, AVL and MT-CMOS, at 180nm CMOS technology to achieve enhancements in delay, power consumption and performance. The proposed circuits are simulated and the results obtained have been analyzed to show significant improvement over conventional SRAM designs. Cadence Virtuoso simulation is used to confirm all the results obtained in this paper for the simulation of 180 nm CMOS technology SRAMs.

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