scholarly journals Electrostatic Characteristics of High-k Stacked Gate-All-Around Heterojunction Tunnel Field Effect Transistor using Superposition Principle

2021 ◽  
Author(s):  
usha C ◽  
P Vimala ◽  
K Ramkumar ◽  
V.N. Ramakrishnan
Keyword(s):  
Surface Potential ◽  
Superposition Principle ◽  
Drain Current ◽  
Superposition Method ◽  
High K ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
Set Up ◽  
Channel Region

Abstract We use superposition method to model the electrostatic characteristics of high-k stacked Gate-All-Around Hetero Junction TFETs (GAA-HJTFETs). The hetero junction is set up by using Ge/Si material in the source/channel respectively. The modeling is accomplished by considering the space charge regions at the source-channel/drainchannel junctions and the channel region. The surface potential in the channel region is obtained by applying superposition principle, where as in source/drain it is derived by solving 2-D/1-D Poisson's equation respectively. Furthermore, the electric field and drain current are modeled from the surface potential and Kane model respectively. The results are confirmed using ATLAS TCAD simulation.

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

2021 ◽  
Author(s):  
SHIKHA U S ◽  
Rekha K James ◽  
Jobymol Jacob ◽  
Anju Pradeep
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Negative Capacitance ◽  
Double Gate ◽  
High K ◽  
Gate Control ◽  
Effect Transistor ◽  
Dimensional Simulation ◽  
The Impact ◽  
Low K

Abstract The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

scholarly journals High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 75 ◽  
Author(s):  
Xiaoling Duan ◽  
Jincheng Zhang ◽  
Jiabo Chen ◽  
Tao Zhang ◽  
Jiaduo Zhu ◽  
...  
Keyword(s):  
Energy Band ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Energy Band Structure ◽  
Drain Region ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Silvaco Atlas ◽  
Channel Region

A drain engineered InGaN heterostructure tunnel field effect transistor (TFET) is proposed and investigated by Silvaco Atlas simulation. This structure uses an additional metal on the drain region to modulate the energy band near the drain/channel interface in the drain regions, and increase the tunneling barrier for the flow of holes from the conduction band of the drain to the valence band of the channel region under negative gate bias for n-TFET, which induces the ambipolar current being reduced from 1.93 × 10−8 to 1.46 × 10−11 A/μm. In addition, polar InGaN heterostructure TFET having a polarization effect can adjust the energy band structure and achieve steep interband tunneling. The average subthreshold swing of the polar drain engineered heterostructure TFET (DE-HTFET) is reduced by 53.3% compared to that of the nonpolar DE-HTFET. Furthermore, ION increases 100% from 137 mA/mm of nonpolar DE-HTFET to 274 mA/mm of polar DE-HTFET.

scholarly journals Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 30 ◽  
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Garam Kim ◽  
Sangwan Kim ◽  
Byung-Gook Park
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Performance ◽  
Control Group ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
High Level ◽  
Aided Design

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results.

Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- $\kappa$ Gate Dielectrics

2009 ◽  
Vol 56 (1) ◽  
pp. 100-108 ◽  
Author(s):  
Martin Schlosser ◽  
Krishna K. Bhuwalka ◽  
Martin Sauter ◽  
Thomas Zilbauer ◽  
Torsten Sulima ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Dielectrics ◽  
Drain Current ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor
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