A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques

2021 ◽  
Vol 14 ◽  
Author(s):  
Selvakumar Rajendran ◽  
Arvind Chakrapani ◽  
Srihari Kannan ◽  
Abdul Quaiyum Ansari
Keyword(s):  
Building Blocks ◽  
Cmos Technology ◽  
Data Converters ◽  
Floating Gate ◽  
Oxide Semiconductor ◽  
Current Mirror ◽  
Mixed Signal ◽  
Advantages And Disadvantages ◽  
Current Mirrors ◽  
Mixed Signal Circuits

Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in µm and nm technology. Current mirror (CM) is a basic building block used to enhance performance characteristics by constructing the complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse of applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technology based current mirror (CM) circuits are discussed with their advantages and disadvantages accompanied by the performance analysis of different parameters. It also briefs on the various techniques which are employed for improvising the current mirror performance like gain boosting and bandwidth extension. Besides, this paper lists the CMs that use different types of MOS devices like Floating Gate MOS, Bulk-driven MOS, and Quasi-Floating Gate MOS. As a result, the paper performs a detailed review on CMOS Current mirrors and its techniques. Results: Basic CM circuits that can act as building blocks in the VLSI circuits are simulated using 0.25 μm, BSIM and Level 1 technology. In addition, various devices based CMs are investigated and compared. Conclusion: The comprehensive discussion shows that the current mirror plays a significant role in analog/mixed-signal circuits design to realize complex systems for low-power biomedical and wireless applications.

scholarly journals Design and Characteristics of CMOS Inverter based on Multisim and Cadence

2021 ◽  
Vol 2108 (1) ◽  
pp. 012034
Author(s):  
Haoran Xu ◽  
Jianghua Ding ◽  
Jian Dang
Keyword(s):  
Metal Oxide ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Data Converters ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Inverter ◽  
And Performance

Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.

scholarly journals Design and analysis of current mirror OTA in 45 nm and 90 nm CMOS technology for bio-medical application

2020 ◽  
Vol 9 (1) ◽  
pp. 221-228
Author(s):  
Wan Mohammad Ehsan Aiman Wan Jusoh ◽  
Siti Hawa Ruslan
Keyword(s):  
Detection System ◽  
Complementary Metal Oxide Semiconductor ◽  
Medical Application ◽  
Cmos Technology ◽  
Open Loop ◽  
Oxide Semiconductor ◽  
Current Mirror ◽  
Ecg Signals ◽  
Transconductance Amplifier ◽  
And Performance

This paper proposed a design and performance analysis of current mirror operational transconductance amplifier (OTA) in 45 nm and 90 nm complementary metal oxide semiconductor (CMOS) technology for bio-medical application. Both OTAs were designed and simulated using Synopsys tools and the simulation results were analysed thoroughly. The OTAs were designed to be implemented in bio-potential signals detection system where the input signals were amplified and filtered according to the specifications. From the comparative analysis of both OTAs, the 45 nm OTA managed to produce open loop gain of 45 dB, with common mode rejection ratio (CMRR) of 93.2 dB. The 45 nm OTA produced only 1.113 μV√Hz of input referred noise at 1 Hz. The 45 nm OTA also consumed only 28.21 nW of power from ± 0.5 V supply. The low-power consumption aspect displayed by 45 nm OTA made it suitable to be implemented in bio-medical application such as bio-potential signals detection system where it can be used to amplify and filter the electrocardiogram (ECG) signals.

scholarly journals Inkjet-printed low-dimensional materials-based complementary electronic circuits on paper

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Irene Brunetti ◽  
Lorenzo Pimpolari ◽  
Silvia Conti ◽  
Robyn Worsley ◽  
Subimal Majee ◽  
...  
Keyword(s):  
Hexagonal Boron Nitride ◽  
Flexible Substrate ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Building Blocks ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wearable Electronics ◽  
Low Dimensional ◽  
Low Dimensional Materials

AbstractComplementary electronics has represented the corner stone of the digital era, and silicon technology has enabled this accomplishment. At the dawn of the flexible and wearable electronics age, the seek for new materials enabling the integration of complementary metal-oxide semiconductor (CMOS) technology on flexible substrates, finds in low-dimensional materials (either 1D or 2D) extraordinary candidates. Here, we show that the main building blocks for digital electronics can be obtained by exploiting 2D materials like molybdenum disulfide, hexagonal boron nitride and 1D materials such as carbon nanotubes through the inkjet-printing technique. In particular, we show that the proposed approach enables the fabrication of logic gates and a basic sequential network on a flexible substrate such as paper, with a performance already comparable with mainstream organic technology.

scholarly journals A Low Input Referred Noise Dynamic Comparator for High Speed Applications

2019 ◽  
Vol 8 (4) ◽  
pp. 4768-4772
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Pivotal Role ◽  
Clock Frequency ◽  
Output Stage ◽  
Dynamic Comparator ◽  
Mixed Signal ◽  
Low Input ◽  
Mixed Signal Circuits ◽  
Amplifier Stage

Comparators play a pivotal role in design of analog and mixed signal circuits. Comparators employ regenerative feedback both in input pre-amplifier stage and output stage. The designed comparator resolves 5mV with resolution of 8 bits and dissipates 11mW of power using 1.2V supply in 130nm CMOS technology while operating at clock frequency of 1.25 GHz

scholarly journals A Bulk-Driven Quasi-Floating Gate Regulated Cascode Current Mirror and Its Application in Squarer Circuit

2022 ◽  
Author(s):  
bchir bchir ◽  
Mounira Bchir ◽  
Imen Aloui ◽  
Nejib Hassen
Keyword(s):  
Performance Improvement ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Floating Gate ◽  
Input Current ◽  
Current Mirror ◽  
Transfer Error ◽  
Simulation Results ◽  
Cascode Current Mirror

Abstract A regulated cascode current mirror (RGC) and its improved version with bulk driven quasi floating gate technique (BD-QFG) are presented in this paper. The proposed BD-QFG RGC current mirror (CM) is compared with the conventional (GD) RGC CM to show the performance improvement. The conventional and unconventional CM are implemented in Candace Virtuoso using 90 nm CMOS technology. For input current (Iin) varied from 0 to 200 μA and for 0.8 V supply voltage, the simulation results present that the proposed BD-QFG RGC CM has less variation in current transfer error (0.2%) as compared to the GD RGC CM (12%). The output voltage requirement for 200 µA input current is respectively 0.7 V and 0.17 V for the GD RGC CM and the BD-QFG RGC CM. The power consumption of the proposed circuit is 22.71 μW which is 0.15 μW higher than the GD RGC (22.56 μW). The total harmonic distortion (THD) of the proposed circuit is 0.4% which is 1.1% less than the conventional circuit (1.5%). All these improvements in the proposed BD-QFG RGC CM are attained at a cost of 0.05 GHz reduction in frequency (2.31 GHz). The minimum supply voltage of BD-QFG RGC CM and GD RGC CM is 0.4 V and

AN IMPROVED ELEMENTARY PROCESSING UNIT FOR HIGH-DENSITY CNN-BASED MIXED-SIGNAL MICROPROCESSORS FOR VISION

2003 ◽  
Vol 12 (06) ◽  
pp. 675-690
Author(s):  
G. LIÑÁN-CEMBRANO ◽  
S. ESPEJO ◽  
R. DOMÍNGUEZ-CASTRO ◽  
A. RODRÍGUEZ-VÁZQUEZ
Keyword(s):  
Focal Plane ◽  
Building Blocks ◽  
Cmos Technology ◽  
High Density ◽  
Processing Unit ◽  
Digital Interface ◽  
Mixed Signal ◽  
On Chip

This paper presents the architecture of the Elementary Processing Unit — EPU — which has been employed to design a CNN-Based 128×128 Focal Plane Mixed-Signal Microprocessor for vision. The EPU contains the required building blocks to implement, on chip, vision algorithms based on the execution of linear 3×3 convolution masks,1 or information propagative CNN templates.2 Using this EPU, we have designed a prototype, called ACE16k, which contains an array of 128×128 EPUs and a completely digital interface, in a standard fully-digital 0.35 μm CMOS technology. The estimation results forecast 300 GOPS, 3.23 GOPS/mm2 and 100 GOP/J.

scholarly journals Towards a generic operational amplifier with dynamic reconfiguration capability

2006 ◽  
Vol 4 ◽  
pp. 259-262
Author(s):  
S. K. Lakshmanan ◽  
A. Koenig
Keyword(s):  
Operational Amplifier ◽  
Building Blocks ◽  
Cmos Technology ◽  
Mixed Signal ◽  
Programmable Analog ◽  
Single Instance ◽  
Field Programmable ◽  
Block Level ◽  
Industrial Standards ◽  
The Impact

Abstract. Analog and analog-digital mixed signal electronics needed for sensor systems are indispensable components which tend to drifts from the normal phase of operation due to the impact of manufacturing conditions and environmental influences like etching, aging etc. Precise design methodology, trimming / calibration are essential to restore functionality of the system. Recent block level granular approaches using Field Programmable Analog Array and the more recent approaches from evolutionary electronics providing transistor level granularity using Field Programmable Transistor Arrays offers considerable extensions. In our work, we started on a new medium granular level approach called Field Programmable medium-granular Mixed-signal Array (FPMA) providing basic building blocks of heterogeneous array of active and passive devices to configure established circuit structures which are adaptive, biologically inspired and dynamically re-configurable. Our design objective is to create components of clear compatibility to that of the industrial standards having predictable behavior along with the incorporation of existing design knowledge. The cells can be used in as a single instance or multiple instances. Further, we will focus on a generic dynamic reconfigurable amplifier cell with flexible topology and dimension called Generic Operational Amplifier (GOPA). The incentive of our work comes from recent development in the field of measurement and instrumentation. The digital programming of analog devices is carried out using range of algorithms from simple to evolutionary. Physical realization of the basic cells is carried out in 0.35 μm CMOS technology.

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