scholarly journals A Low Input Referred Noise Dynamic Comparator for High Speed Applications

2019 ◽  
Vol 8 (4) ◽  
pp. 4768-4772
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Pivotal Role ◽  
Clock Frequency ◽  
Output Stage ◽  
Dynamic Comparator ◽  
Mixed Signal ◽  
Low Input ◽  
Mixed Signal Circuits ◽  
Amplifier Stage

Comparators play a pivotal role in design of analog and mixed signal circuits. Comparators employ regenerative feedback both in input pre-amplifier stage and output stage. The designed comparator resolves 5mV with resolution of 8 bits and dissipates 11mW of power using 1.2V supply in 130nm CMOS technology while operating at clock frequency of 1.25 GHz

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

2019 ◽  
Vol 29 (06) ◽  
pp. 2050084
Author(s):  
Daiguo Xu ◽  
Hequan Jiang ◽  
Dongbin Fu ◽  
Xiaoquan Yu ◽  
Shiliu Xu ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Low Noise ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Input Noise ◽  
Clock Feedthrough ◽  
Threshold Voltages ◽  
Coupled Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

A Low-Noise Dynamic Comparator with Offset Calibration for CMOS Image Sensor Architecture

2018 ◽  
Vol 28 (02) ◽  
pp. 1950022
Author(s):  
Arumugam Sathishkumar ◽  
Siddhan Saravanan
Keyword(s):  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Low Noise ◽  
Clock Frequency ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Input Capacitance ◽  
Simulation Results ◽  
Output Swing

A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-rail output swing is also improved. The input capacitance is reduced by using shared first-stage technique. The comparator is designed with constant [Formula: see text]/[Formula: see text] biasing to suppress the environmental drift. The simulation results from 45-nm and 65-nm CMOS technologies confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 3.5[Formula: see text]GHz and 2.2[Formula: see text]GHz at supply voltages of 1[Formula: see text]V and 0.6[Formula: see text]V, respectively. Simulations are carried out using predictive technology models for 45[Formula: see text]nm and 65[Formula: see text]nm in HSPICE.

A 0.5–1.2 V PWM CMOS DPS WITH 120 dB DYNAMIC RANGE FOR BIONIC HUMAN EYE IN DEEP SUBMICRON CMOS TECHNOLOGY

2014 ◽  
Vol 23 (02) ◽  
pp. 1450020 ◽  
Author(s):  
JIANGTAO XU ◽  
WEISONG JIN ◽  
KAIMING NIE ◽  
SUYING YAO
Keyword(s):  
High Speed ◽  
Pulse Width Modulation ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Digital Camera ◽  
Cmos Technology ◽  
Frame Rate ◽  
Clock Frequency ◽  
Human Eye ◽  
Digital Pixel

In this paper, a CMOS digital pixel sensor (DPS) with pixel-level ADC based on pulse width modulation (PWM) scheme is proposed to overcome the restriction of low supply voltage imposed by device scaling trend. The pixel operates with a dynamic current comparison scheme to avoid using complex in-pixel comparator and achieve a high dynamic range (DR). By adjusting clock frequency for different illumination, DR is further extended due to increasing the maximum detectable photocurrent and lowering the minimum detectable photocurrent. The pixel contains a photodiode (PD), an 11-bit in-pixel SRAM and other 11 transistors, and occupies an area of 7 μm × 7 μm, with a fill factor of 31.3% using a standard 65 nm CMOS technology. Simulation results show that this pixel can work at a supply voltage as low as 0.5 V with 120 dB DR and 80 dB linear DR (LDR). The properties of high DR and logarithmic response make the proposed digital pixel be capable of human eye. Frame rate achieves 246 fps with 640 × 480 pixel array by using in-pixel ADC and SRAM. This makes the digital pixel very suitable for high-speed snap shot digital camera application.

A ROBUST HIGH-SPEED LOW INPUT IMPEDANCE CMOS CURRENT COMPARATOR

2008 ◽  
Vol 17 (06) ◽  
pp. 1139-1149 ◽  
Author(s):  
VARAKORN KASEMSUWAN ◽  
SURACHET KHUCHAROENSIN
Keyword(s):  
Input Impedance ◽  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Circuit Performance ◽  
Current Comparator ◽  
Low Input ◽  
Voltage Conversion

In this paper, a robust high-speed low input impedance CMOS current comparator is proposed. The front end of the comparator uses the modified Wilson current-mirror and diode-connected transistors to perform a current subtraction and current to voltage conversion simultaneously. The circuit is immune to the process variation and has low input impedances. HSPICE is used to verify the circuit performance with a 0.5 μm CMOS technology. The simulation results show the propagation delay of 1.67 ns, input impedances of 123 Ω, and 126 Ω, and average power dissipation of 0.63 mW for ± 0.1 μA input current under the supply voltage of 3 V.

scholarly journals Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style

2016 ◽  
Vol 2016 ◽  
pp. 1-10
Author(s):  
Neeta Pandey ◽  
Damini Garg ◽  
Kirti Gupta ◽  
Bharat Choudhary
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
Current Mode ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Mixed Signal ◽  
Current Mode Logic ◽  
Digital Circuit Design ◽  
Pass Transistor ◽  
Logic Functions

This paper proposes hybrid dynamic current mode logic (H-DyCML) as an alternative to existing dynamic CML (DyCML) style for digital circuit design in mixed-signal applications. H-DyCML introduces complementary pass transistors for implementation of logic functions. This allows reduction in the stacked source-coupled transistor pair levels in comparison to the existing DyCML style. The resulting reduction in transistor pair levels permits significant speed improvement. SPICE simulations using TSMC 180 nm and 90 nm CMOS technology parameters are carried out to verify the functionality and to identify their advantages. Some issues related to the compatibility of the complementary pass transistor logic have been investigated and the appropriate solutions have been proposed. The performance of the proposed H-DyCML gates is compared with the existing DyCML gates. The comparison confirms that proposed H-DyCML gates is faster than the existing DyCML gates.

Design of a SoC With High-Speed DDC for Software Radio Receiver

2012 ◽  
Vol 605-607 ◽  
pp. 1875-1879 ◽  
Author(s):  
Jun Deng ◽  
Lin Tao Liu ◽  
Yu Jing Li ◽  
Xiao Zong Huang ◽  
Xu Huang ◽  
...  
Keyword(s):  
High Speed ◽  
Software Radio ◽  
Intermediate Frequency ◽  
Cmos Technology ◽  
Radio Receiver ◽  
Clock Frequency ◽  
Baseband Signal ◽  
Baseband Signal Processing ◽  
Good Potential ◽  
On Chip

This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.

Sign in / Sign up

Export Citation Format

Share Document