scholarly journals Development of a prototype front-end board of the Thin Gap Chamber for ATLAS at the High-Luminosity LHC

2017 ◽  
Author(s):  
Tomomi Kawaguchi ◽  
Kotoko Shukutani
Keyword(s):  
High Luminosity ◽  
Front End

scholarly journals Comparative evaluation of analogue front-end designs for the CMS Inner Tracker at the High Luminosity LHC

2021 ◽  
Vol 16 (12) ◽  
pp. P12014
Author(s):  
W. Adam ◽  
T. Bergauer ◽  
D. Blöch ◽  
M. Dragicevic ◽  
R. Frühwirth ◽  
...  
Keyword(s):  
High Efficiency ◽  
Low Noise ◽  
Pixel Detector ◽  
High Luminosity ◽  
Advantages And Disadvantages ◽  
High Particle ◽  
Front End ◽  
Improved Design ◽  
Threshold Tuning ◽  
Radiation Tolerant

Abstract The CMS Inner Tracker, made of silicon pixel modules, will be entirely replaced prior to the start of the High Luminosity LHC period. One of the crucial components of the new Inner Tracker system is the readout chip, being developed by the RD53 Collaboration, and in particular its analogue front-end, which receives the signal from the sensor and digitizes it. Three different analogue front-ends (Synchronous, Linear, and Differential) were designed and implemented in the RD53A demonstrator chip. A dedicated evaluation program was carried out to select the most suitable design to build a radiation tolerant pixel detector able to sustain high particle rates with high efficiency and a small fraction of spurious pixel hits. The test results showed that all three analogue front-ends presented strong points, but also limitations. The Differential front-end demonstrated very low noise, but the threshold tuning became problematic after irradiation. Moreover, a saturation in the preamplifier feedback loop affected the return of the signal to baseline and thus increased the dead time. The Synchronous front-end showed very good timing performance, but also higher noise. For the Linear front-end all of the parameters were within specification, although this design had the largest time walk. This limitation was addressed and mitigated in an improved design. The analysis of the advantages and disadvantages of the three front-ends in the context of the CMS Inner Tracker operation requirements led to the selection of the improved design Linear front-end for integration in the final CMS readout chip.

scholarly journals An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1760
Author(s):  
Folla Kamdem Jérôme ◽  
Wembe Tafo Evariste ◽  
Essimbi Zobo Bernard ◽  
Maria Liz Crespo ◽  
Andres Cicuttin ◽  
...  
Keyword(s):  
Low Power ◽  
High Throughput ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
High Luminosity ◽  
Gain Bandwidth ◽  
Wide Bandwidth ◽  
Ultra Low Power ◽  
Front End

The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

scholarly journals A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

2018 ◽  
Vol 170 ◽  
pp. 01015
Author(s):  
Sergey Senkin
Keyword(s):  
Signal Reconstruction ◽  
Real Data ◽  
Cmos Technology ◽  
Injection System ◽  
Atlas Collaboration ◽  
Reconstruction Method ◽  
Optimal Filtering ◽  
Beam Test ◽  
High Luminosity ◽  
Front End

The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

scholarly journals The VFAT3-Comm-Port: a complete communication port for front-end ASICs intended for use within the high luminosity radiation environments of the LHC

2015 ◽  
Vol 10 (03) ◽  
pp. C03019-C03019 ◽  
Author(s):  
M. Dabrowski ◽  
P. Aspell ◽  
S. Bonacini ◽  
D. Ciaglia ◽  
G. De Lentdecker ◽  
...  
Keyword(s):  
High Luminosity ◽  
Front End

scholarly journals Design and test of current-mode DACs for threshold tuning of front-end channels for the High Luminosity LHC

2020 ◽  
Author(s):  
Luigi Gaioni ◽  
M. Manghisoni ◽  
L. Ratti ◽  
V. Re ◽  
G. Traversi
Keyword(s):  
Current Mode ◽  
High Luminosity ◽  
Front End ◽  
Threshold Tuning

scholarly journals Upgrade of the ATLAS Hadronic Tile Calorimeter for the High Luminosity LHC

2018 ◽  
Vol 170 ◽  
pp. 01001
Author(s):  
Ignacio Asensi Tortajada
Keyword(s):  
Current System ◽  
Hadron Collider ◽  
Data Acquisition System ◽  
Final Solution ◽  
High Luminosity ◽  
Trigger System ◽  
Test Beam ◽  
Particle Beams ◽  
Front End ◽  
The Status

The Large Hadron Collider (LHC) has envisaged a series of upgrades towards a High Luminosity LHC (HL-LHC) delivering five times the LHC nominal instantaneous luminosity. The ATLAS Phase II upgrade, in 2024, will accommodate the upgrade of the detector and data acquisition system for the HL-LHC. The Tile Calorimeter (TileCal) will undergo a major replacement of its on- and off-detector electronics. In the new architecture, all signals will be digitized and then transferred directly to the off-detector electronics, where the signals will be reconstructed, stored, and sent to the first level of trigger at the rate of 40 MHz. This will provide better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. Changes to the electronics will also contribute to the reliability and redundancy of the system. Three different front-end options are presently being investigated for the upgrade, two of them based on ASICs, and a final solution will be chosen after extensive laboratory and test beam studies that are in progress. A hybrid demonstrator module is being developed using the new electronics while conserving compatibility with the current system. The status of the developments will be presented, including results from the several tests with particle beams.

scholarly journals A program to drive the ATLAS Local Trigger Interface (ALTI) at the ATLAS experiment

2021 ◽  
Vol 2105 (1) ◽  
pp. 012024
Author(s):  
Foteini Trantou
Keyword(s):  
Data Analysis ◽  
Phase 1 ◽  
Optical Network ◽  
Hadron Collider ◽  
Normal Operation ◽  
High Luminosity ◽  
Atlas Experiment ◽  
Front End ◽  
Physics Performance ◽  
And Control

Abstract During the High Luminosity upgrade of the Large Hadron Collider at CERN, the LHC experiments will undergo a series of upgrades in order to maintain high physics performance following an increased data rate. The largest Phase 1 upgrade project at the ATLAS muon system is the replacement of the current inner station (end-cap regions) with the New Small Wheels. In addition, the ATLAS Local Trigger Interface (ALTI), a part of the Timing, Trigger and Control (TTC) system, will replace the four existing TTC modules. In normal operation, the detectors, along with the surrounding electronics, will receive TTC related signals from the Central Trigger Processor (CTP). This information is forwarded to the front-end electronics of each of the ATLAS sub-detectors through an optical network via the ALTI. The interface currently produces an artificially generated pulse pattern that contains the TTC information. This paper will summarize the creation of a program that generates pulse pattern files which are used to drive ALTI. Various tests have been conducted in order to study the performance of the NSW trigger electronics while using these files. Software development and data analysis using ROOT framework were used to validate the results of these tests.

scholarly journals Upgrade of the CMS resistive plate chambers for the high luminosity LHC

2022 ◽  
Vol 17 (01) ◽  
pp. C01011
Author(s):  
A. Samalan ◽  
M. Tytgat ◽  
G.A. Alves ◽  
F. Marujo ◽  
F. Torres Da Silva De Araujo ◽  
...  
Keyword(s):  
Large Hadron Collider ◽  
Compact Muon Solenoid ◽  
Hadron Collider ◽  
Present System ◽  
High Luminosity ◽  
Readout System ◽  
Experimental Conditions ◽  
Cms Experiment ◽  
Front End ◽  
Resistive Plate Chambers

Abstract During the upcoming High Luminosity phase of the Large Hadron Collider (HL-LHC), the integrated luminosity of the accelerator will increase to 3000 fb−1. The expected experimental conditions in that period in terms of background rates, event pileup, and the probable aging of the current detectors present a challenge for all the existing experiments at the LHC, including the Compact Muon Solenoid (CMS) experiment. To ensure a highly performing muon system for this period, several upgrades of the Resistive Plate Chamber (RPC) system of the CMS are currently being implemented. These include the replacement of the readout system for the present system, and the installation of two new RPC stations with improved chamber and front-end electronics designs. The current overall status of this CMS RPC upgrade project is presented.

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