scholarly journals Fully Integrated K-Band Active Bandpass Filter In GPDK 90nm CMOS Technology

2018 ◽  
Vol 11 (1) ◽  
pp. 3-6
Author(s):  
Md. Jamil Uddin ◽  
Hadaate Ullah ◽  
Mohammad Arif Sobhan Bhuiyan
Keyword(s):  
Quality Factor ◽  
Circuit Design ◽  
Bandpass Filter ◽  
Noise Figure ◽  
Cmos Technology ◽  
Active Inductor ◽  
Rf Transceiver ◽  
Chip Area ◽  
Fully Integrated ◽  
Chip Size

Abstract The bandpass filter is one of the essential blocks of every modern RF transceiver. Performance of the transceiver greatly depends on the performance of the bandpass filter. A bandpass filter designed with passive inductors suffers from some drawbacks like large chip size, low-quality factor, less tenability etc. To prevail over these constraints, an active inductor-based bandpass filter circuit has been designed in GPDK-90nm CMOS technology utilizing cadence virtuoso environment. The simulation result shows that the active inductor-based bandpass filter circuit design achieves a gain of 6.79dB, a bandwidth of 5.05 GHz and a noise figure of 3.10dB. The circuit dissipates only 3.55mW power for its operation from a single 1.5V DC supply. By avoiding bulky inductor in the design helped to attain a very small chip area of 127.704μm2.

60 GHz-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi
Keyword(s):  
Transmission Line ◽  
Quality Factor ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Constant Current ◽  
60 Ghz ◽  
Frequency Range ◽  
Constant Current Density ◽  
Chip Area

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

A 5.8GHz Band-Pass Filter With an Active Inductor Through 0.18μm Full-CMOS Process for Wireless Transceivers

2007 ◽  
Author(s):  
Mu-Chun Wang ◽  
Zhen-Ying Hsieh ◽  
Cheng-Yi Ke ◽  
Shuang-Yuan Chen ◽  
Heng-Sheng Huang
Keyword(s):  
Return Loss ◽  
Bandpass Filter ◽  
Noise Figure ◽  
Simulation Software ◽  
Process Models ◽  
Active Inductor ◽  
Cmos Process ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Chip Area

Substituting the active inductor for the passive inductor to integrate the 5.8GHz bandpass filter into a system-on-chip (SoC) circuit is a feasible solution to reduce the filter chip area, increasing the application competition. The bandpass filter circuit in simulation with TSMC 0.18um CMOS process models and Agilent simulation software exhibits the good performance such as an input return loss (S11) of −34.26dB, an output return loss (S22) of −17.49dB, a bandpass gain (S21) of −4.33dB, a noise figure (NF) of 18.91dBm, a 1-dB compression point (P1dB) of −23dBm, a third-order intercept point (IIP3) of −15.83dBm, and the power dissipation in 19.44mW under 1.8V power-supply operation. In addition, the 3-dB bandpass bandwidth is 300MHz. The final dimension of this chip is approximate to 680×530μm2.

scholarly journals Ultra-Wide Band LNA Design using Active Inductor with Modified Noise Cancellation Technique

2019 ◽  
Vol 8 (2) ◽  
pp. 2406-2410
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Ultra Wide Band ◽  
Active Inductor ◽  
Cmos Process ◽  
Chip Area ◽  
Chip Size ◽  
Lna Design

An Ultra-Wide Band (UWB) Low Noise Amplifier (LNA) is affective in deciding the chip size and in the implementation cost at Radio Frequency applications. The proposed LNA design with an active inductor is a different solution to trounce the habit of passive inductors to cut the chip area. Designed in 90-nm CMOS process, a voltage gain of 9dB to 15.5dB for a supply voltage of 0.9v to 1.8V with a smallest Noise Figure (NF) of 5.7dB is achieved by the LNA, with low power utilization and at 2.40 GHz, with 345um2 of chip area.

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

A 9 dB Noise Figure Fully Integrated 79 GHz Automotive Radar Receiver in 40 nm CMOS Technology

2019 ◽  
Author(s):  
Tomotoshi Murakami ◽  
Nobumasa Hasegawa ◽  
Yoshiyuki Utagawa ◽  
Tomoyuki Arai ◽  
Shinji Yamaura
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Automotive Radar ◽  
Fully Integrated

Tunable CMOS Active Inductor Using Widlar Current Source

2018 ◽  
Vol 28 (02) ◽  
pp. 1950027 ◽  
Author(s):  
Dhara P Patel ◽  
Shruti Oza-Rahurkar
Keyword(s):  
Quality Factor ◽  
Supply Voltage ◽  
Noise Analysis ◽  
Current Source ◽  
Cmos Technology ◽  
The Other ◽  
Active Inductor ◽  
Voltage Sensitivity ◽  
Current Mirror ◽  
Characterization Factors

A novel tuning principle for simple gyrator-based CMOS active inductor (AI) circuit is presented. The method makes use of Widlar current source to enhance the quality factor. The simulation of the proposed AI provides a maximum quality factor of 1819 at 2.88[Formula: see text]GHz. The AI shows the inductive bandwidth of 1.66[Formula: see text]GHz to 3.16[Formula: see text]GHz and power consumption of 6.87[Formula: see text]mW. The other characterization factors such as linearity, supply voltage sensitivity and noise analysis are discussed. The performance of the tunable AI using Widlar current source are compared with the same using a simple current mirror. An AI using a conventional current mirror (CCM) and Widlar current source have been implemented in the 0.18[Formula: see text][Formula: see text]m CMOS technology.

scholarly journals Research and Design of X-band Low Noise Amplifier Based on CMOS Process

2021 ◽  
Vol 2108 (1) ◽  
pp. 012102
Author(s):  
Chao Ma ◽  
Hongjiang Wu ◽  
Xudong Lu ◽  
Haitao Sun
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Center Frequency ◽  
Cmos Process ◽  
Actual Measurement ◽  
Chip Area ◽  
Chip Size ◽  
Noise Amplifier ◽  
Stage Matching

Abstract Based on CMOS process, a low noise amplifier(LNA) operating at 7.4GHz~11.4GHz was designed. The two-stage differential cascode structure is adopted. Transformer was used to achieve inter-stage matching. Balun was used to achieve input and output matching, which reduces the number of inductors used, effectively reduces the chip size while ensuring good gain and noise figure. The actual measurement results show that the power gain at the center frequency of 9.4GHz is 27dB, the maximum noise figure is less than 3.82dB, the output power 1dB compression point is greater than 8dBm, the chip area is only 0.41mm×0.83mm(excluding PAD).

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